Abstract: According to one embodiment, a memory system includes a first storage area and a controller. The first storage area configured to store therein data sent from a host. The size of the first storage area is a first size larger than a second size. The second size is a size of a logical address space which is assigned to a memory system by the host. The controller is configured to change the second size in response to a request from the host while at least a part of data in the logical address space stays valid.

Abstract: According to one embodiment, there is provided a memory system including a volatile memory and a controller. The volatile memory has 1st to Kth memory banks (K is a natural number equal to or larger than 2) that are kept in a power-on state and (K+1)th to Nthmemory banks (N is a natural number larger than K) whose power state is changed. The power state is the power-on state or a power-down state. The controller performs wake-up operation for the (K+1)th to Nth memory banks in parallel with access operation to the 1st to Kth memory banks. The wake-up operation changes the power state from the power-down state to the power-on state.

Abstract: According to one embodiment, a memory system includes a first storage area and a controller. The first storage area configured to store therein data sent from a host. The size of the first storage area is a first size larger than a second size. The second size is a size of a logical address space which is assigned to a memory system by the host. The controller is configured to change the second size in response to a request from the host while at least a part of data in the logical address space stays valid.

Abstract: According to one embodiment, a memory control device includes: queues in channels; first controller; generator; and second controller. The queues hold write commands for data pieces. The first controller causes: (i) when a read command is received, and until the write commands are held in the queues, the channels are synchronized with each other, and processes of the write commands become ready to be performed, a read process based on the read command prior to the write commands; and, (ii) when the processes of write commands become ready to be performed, synchronization of the channels and write processes for the data pieces based on the write commands. The generator generates error correction codes based on the data pieces when the channels are synchronized with each other and the processes based on the write commands are performed. The second controller writes the error correction codes on the storage medium.

Abstract: According to one embodiment, there is provided a memory system including a volatile memory and a controller. The volatile memory has 1st to Kth memory banks (K is a natural number equal to or larger than 2) that are kept in a power-on state and (K+1)th to Nth. memory banks (N is a natural number larger than K) whose power state is changed. The power state is the power-on state or a power-down state. The controller performs wake-up operation for the (K+1)th to Nth memory banks in parallel with access operation to the 1st to Kth memory banks. The wake-up operation changes the power state from the power-down state to the power-on state.

Abstract: A storage device includes a memory having one or more storage regions each of which is assigned a physical address, and a controller having a writing control circuit configured to write data that is divided into a plurality of data units into logical storage positions, at least one of which is associated with two storage regions of the memory, and a conversion unit configured to perform a conversion process on a logical address of the logical storage position that is associated with two storage regions of the memory to generate physical addresses corresponding to the two storage regions of the memory.

Abstract: According to one embodiment, a data storage apparatus includes a read module, an error detector and a controller. The read module is configured to read data from a flash memory, more precisely from a rewrite area and a write-back area, both provided in the flash memory. The error detector is configured to detect errors, if any, in the data read. The controller is configured to keep rewriting data, without correcting the errors the error detector has detected in the rewrite area of the flash memory.

Abstract: According to one embodiment, a data storage apparatus includes a flash memory and a controller for controlling the flash memory. The flash memory is configured to store data is written in units of a prescribed size. In order to write data smaller than the prescribe size, the controller first isolates attribute data from each save data item of the prescribed size, which has been read from any flash memory, and then stores the attribute data to an attribute data memory, and finally transfers the user data contained in the save data, to a save data memory.

Abstract: According to one embodiment, a data storage apparatus includes a memory module and a controller. The memory module has a plurality of flash memory chips. Data is written to or read from each flash memory chip having a specific page size as access unit. The controller is configured to supply memory control signals, which are independent of the common signal containing the data and addresses, to the flash memory chips, respectively, in order to write data larger than the specific data size to the memory module. In the memory module, the respective flash memory chips store the data, each at the same address, in response to the memory control signals.

Abstract: According to one embodiment, a memory control device includes: queues in channels; first controller; generator; and second controller. The queues hold write commands for data pieces. The first controller causes: (i) when a read command is received, and until the write commands are held in the queues, the channels are synchronized with each other, and processes of the write commands become ready to be performed, a read process based on the read command prior to the write commands; and, (ii) when the processes of write commands become ready to be performed, synchronization of the channels and write processes for the data pieces based on the write commands. The generator generates error correction codes based on the data pieces when the channels are synchronized with each other and the processes based on the write commands are performed. The second controller writes the error correction codes on the storage medium.

Abstract: According to one embodiment, a data storage apparatus includes a read module, an error detector and a controller. The read module is configured to read data from a flash memory, more precisely from a rewrite area and a write-back area, both provided in the flash memory. The error detector is configured to detect errors, if any, in the data read. The controller is configured to keep rewriting data, without correcting the errors the error detector has detected in the rewrite area of the flash memory.

Abstract: According to one embodiment, a data storage apparatus includes a flash memory and a controller for controlling the flash memory. The flash memory is configured to store data is written in units of a prescribed size. In order to write data smaller than the prescribe size, the controller first isolates attribute data from each save data item of the prescribed size, which has been read from any flash memory, and then stores the attribute data to an attribute data memory, and finally transfers the user data contained in the save data, to a save data memory.

Abstract: An integrated circuit includes an AD converter and a self-test circuit configured to test the AD converter. The self-test circuit includes a clock generator which generates a clock for allowing the AD converter to AD-convert an external sine wave signal externally input, a sine wave generator which generates an internal sine wave signal in digital form, a subtractor which determines a differential signal between the AD-converted external sine wave signal and the internal sine wave signal, a PLL device which allows a phase-locked loop receiving the differential signal as an input to control a phase of the internal sine wave signal such that the internal sine wave signal is in phase with the external sine wave signal, and a root mean square calculator which calculates a root mean square of the differential signal to generate a diagnostic signal corresponding to the AD converter.

Abstract: According to one embodiment, a data recording and reproducing apparatus includes: a reproduced signal output device reading data recorded on an optical recording medium to output a reproduced signal; and a waveform compensation amount data generating device generating waveform compensation amount data of a recording waveform corresponding to recording data which is to be recorded to the optical recording medium. At the time of recording learning, this data recording and reproducing apparatus integrates, for each pattern, waveform error data which are used as a basis of the generation of the waveform compensation amount data by the waveform compensation amount data generating device, and adjusts output of a pattern instruction signal for instructing which of the patterns is an integration target, so as to integrate, for each pattern, the waveform error data in a target test write area corresponding to an integer number of rotations of the optical recording medium.

Abstract: An integrated circuit includes an AD converter and a self-test circuit configured to test the AD converter. The self-test circuit includes a clock generator which generates a clock for allowing the AD converter to AD-convert an external sine wave signal externally input, a sine wave generator which generates an internal sine wave signal in digital form, a subtractor which determines a differential signal between the AD-converted external sine wave signal and the internal sine wave signal, a PLL device which allows a phase-locked loop receiving the differential signal as an input to control a phase of the internal sine wave signal such that the internal sine wave signal is in phase with the external sine wave signal, and a root mean square calculator which calculates a root mean square of the differential signal to generate a diagnostic signal corresponding to the AD converter.

Abstract: There is provided a recording apparatus which modulates record data by a predetermined modulation method and records record patterns corresponding to the record data on an optical disk, including a random data generator which generates random data as the record data, a data exchange processor which performs exchange processing on the random data so as to equalize a frequency of appearance of each of the record patterns relative to the entire record patterns on the optical disk corresponding to the respective random data, a modulator which modulates the random data subjected to the exchange processing by the predetermined modulation method, an optical head which records record patterns corresponding to the modulated random data on the optical disk, and reproduces the modulated random data from the recorded record patterns, and a record learning unit which calculates correction amounts for recorded positions of the respective record patterns based on the reproduced random data.

Abstract: According to one embodiment, in an information recording and reproducing apparatus, a record data correction unit generates correction data for correcting a record waveform generated according to record data. Further, the information recording and reproducing apparatus generates discrimination data for use in pattern discrimination performed to generate the correction data, using decoded data outputted from a PRML signal processing unit and the record data, and outputs the generated discrimination data to the record data correction unit.

Abstract: An information reproducing apparatus reads information recorded on a recording medium and outputs a reproduced signal, and performs, for the reproduced signal, analog offset correction of correcting offset before AD conversion, digital offset correction of correcting offset after AD conversion, and offset detection of detecting an offset control amount from a corrected reproduced signal after the digital offset correction. Further, the information reproducing apparatus divides offset data indicating the detected offset control amount into first offset data of a least significant bit unit for the AD conversion of the reproduced signal or greater and second offset data less than the least significant bit unit so as to perform the digital offset correction using the first offset data and perform the analog offset correction using the second offset data.

Abstract: According to one embodiment, there is provided an optical disk apparatus including a detecting unit which reads a reflective light from an optical disk and outputs a read signal, a decoder which decodes the read signal from the detecting unit, an extracting unit which extracts from the read signal the first and second specification information of the same content recorded in first and second areas on the optical disk, a processor which compares the first specification information with the second specification information and processes the specification information based on the comparison result, and a controller which controls the detecting unit or the decoder, based on the specification information processed by the processor.

Abstract: A data processing apparatus may include a memory unit which stores information including sync frame data, a preceding calculation system circuit which makes a syndrome calculation from the information including sync frame data, a retry calculation system circuit which makes a syndrome calculation from information stored in the memory unit, a buffer group which stores a calculation result of the preceding calculation system circuit or that of the retry calculation system circuit, and a correction execution process system circuit which executes error correction for the information including sync frame data according to the calculation result stored in the buffer group.