Abstract: A molded resin product includes a plurality of protrusions formed in a predetermined region. A histogram indicating a height distribution of the plurality of protrusions has two peaks having a boundary height as a boundary therebetween. In a case where protrusions having height equal to or smaller than the height Hx are first protrusions and protrusions having height larger than the boundary height are second protrusions among the plurality of protrusions, an arithmetic mean curvature of the first protrusions is smaller than an arithmetic mean curvature of the second protrusions.

Abstract: Provided is a photoelectric sensor capable of being securely joined to a housing while being sufficiently resistant to dirt. A housing 12 of a photoelectric sensor 10 has an opening 121 which allows passage of at least one of light from a light projecting unit 14 and light to a light receiving unit 16, and is provided with a cover lens 50 which covers the opening 121 and is optically transmissive. The cover lens 50 is joined to an edge portion 121a of the housing 12 defining the opening 121. An outer surface 51 of the cover lens 50 is provided with antifouling coating 61. An inner surface 52 of the cover lens 50 has a joint portion 52a which is in contact with the edge portion 121a and is not provided with the antifouling coating 61.

Abstract: Provided is a photoelectric sensor capable of being securely joined to a housing while being sufficiently resistant to dirt. A housing 12 of a photoelectric sensor 10 has an opening 121 which allows passage of at least one of light from a light projecting unit 14 and light to a light receiving unit 16, and is provided with a cover lens 50 which covers the opening 121 and is optically transmissive. The cover lens 50 is joined to an edge portion 121a of the housing 12 defining the opening 121. An outer surface 51 of the cover lens 50 is provided with antifouling coating 61. An inner surface 52 of the cover lens 50 has a joint portion 52a which is in contact with the edge portion 121a and is not provided with the antifouling coating 61.

Abstract: An abnormality processing system is provided capable of executing appropriate processing in cases where an abnormality occurs in a worker's living body. A management computer 300, if determining that an abnormality is present in a worker's living body, transmits an abnormality signal to an administrator terminal 100, a work device 200, a worker camera 20 and a surveillance camera 50. When receiving the abnormality signal, the administrator terminal 100 displays an image showing that an abnormality has occurred. When receiving the abnormality signal, the work device 200 stops operation. When receiving the abnormality signal, the worker camera 20 and the surveillance camera 50 transmit to the management computer 300 imaging data containing at least data of images before and after a timing at which the abnormality has occurred in the worker's living body.

Abstract: The piezoelectric element includes, on a substrate: a piezoelectric film; and a pair of electrodes provided in contact with the piezoelectric film; in which the piezoelectric film contains a perovskite-type metal oxide represented by the general formula (1) as a main component: Ax(ZnjTi(1-j))l(MgkTi(1-k))mMnO3??General Formula (1) wherein the perovskite-type metal oxide is uniaxially (111)-oriented in pseudo-cubic notation in a thickness direction, of the pair of electrodes, a lower electrode provided on the substrate side is a multilayer electrode including at least a first electrode layer in contact with the substrate and a second electrode layer in contact with the piezoelectric film, and the second electrode layer is a perovskite-type metal oxide electrode which is uniaxially (111)-oriented in pseudo-cubic notation in a thickness direction.

Abstract: The invention prevents a semiconductor device from warping due to heat when it is used. The invention also prevents a formation defect such as peeling of a resist layer used as a plating mask and a formation defect of a front surface electrode. A source pad electrode connected to a source region is formed on a front surface of a semiconductor substrate forming a vertical MOS transistor. A front surface electrode is formed on the source pad electrode by a plating method using a resist layer having openings as a mask. The semiconductor substrate formed with the front surface electrode is thinned by back-grinding. A back surface electrode connected to a drain region is formed on the back surface of the semiconductor substrate. The front surface electrode and the back surface electrode are made of metals having the same coefficients of linear expansion, preferably copper. The front surface electrode and the back surface electrode preferably have the same thicknesses or almost the same thicknesses.

Abstract: This invention is directed to form a homogeneous film in a via hole formed in a semiconductor device using Bosch process. The via hole that penetrates through a predetermined region in a semiconductor substrate is formed by etching the semiconductor substrate from one of its surface to the other by the Bosch process using a mask layer as a mask. Next, the mask layer is removed. Then, scallops are removed by dry etching to flatten a sidewall of the via hole. Following the above, an insulation film, a barrier layer and the like are formed homogeneously in the via hole.

Abstract: The invention provides a method of manufacturing a semiconductor device which achieves high reliability and high yield as well as high production efficiency. Back surface grinding (back grinding) is performed to a semiconductor substrate to thin the semiconductor substrate. A damaged layer formed by the back surface grinding is not removed at this time, and a photoresist layer is selectively formed on the back surface of the semiconductor substrate. The semiconductor substrate is then etched using the photoresist layer as a mask to form a via hole. The photoresist layer is then removed with the semiconductor substrate still placed in an etcher used in the etching process subsequently after the formation of the via hole. In this manner, the etching process and the next ashing process are performed sequentially in one apparatus.

Abstract: The invention is directed to a semiconductor device having a via hole and a method of manufacturing the same that achieve both the prevention of a barrier layer insufficiently covering the via hole and the control of via resistance at the same time. A semiconductor substrate having a pad electrode on its front surface is prepared. The semiconductor substrate is etched from its back surface to its front surface to form a via hole exposing the pad electrode. A first barrier layer is then formed in the via hole by a sputtering method or a PVD method and reverse-sputtering (etching). By this reverse-sputtering, the barrier layer on the bottom of the via hole is removed to expose the pad electrode. A second barrier layer is then formed on the pad electrode exposed in the via hole. The via resistance is controlled by adjusting only the thickness of the second barrier layer.

Abstract: In a power MOS transistor, for example, a source electrode is formed so as to be commonly connected to a plurality of source regions formed on the front surface. Thus, a current density varies based on in-plane resistance of the source electrode, thereby providing the necessity of increasing the number of wires connecting the sources and a lead. In the invention, an electrode structure includes a copper plating layer 10e formed on a pad electrode 10a by an electrolytic plating method, and a nickel plating layer 10f and a gold plating layer formed so as to cover the upper and side surfaces of the copper plating layer 10e by an electroless plating method.

Abstract: The invention is directed to enhancement of reliability and a yield of a semiconductor device by a method of manufacturing the semiconductor device with a supporting body without making the process complex. A second insulation film, a semiconductor substrate, a first insulation film, and a passivation film are etched and removed in this order using a resist layer or a protection layer as a mask. By this etching, an adhesive layer is partially exposed in an opening. At this time, a number of semiconductor devices are separated in individual semiconductor dies. Then, as shown in FIG. 10, a solvent (e.g. alcohol or acetone) is supplied to the exposed adhesive layer through the opening to gradually reduce its adhesion and thereby a supporting body is removed from the semiconductor substrate.

Abstract: The characteristic of the semiconductor device of this invention is that the device has a piercing hole 10 formed in the semiconductor layer to touch a first metal film 18, a insulating film 12 formed on the side wall of the piercing hole 10, a second metal film 13 disposed on the first metal film 18 at the bottom of the piercing hole 10 where the insulating film 12 has not been formed and on the semiconductor layer, a barrier metal film 14 formed on the insulating film 12 in the piercing hole 10 and on the first metal film 18, and a wiring layer 15 formed inside the piercing hole 10 through the barrier metal film 14.

Abstract: The invention prevents a semiconductor device from warping due to heat when it is used. The invention also prevents a formation defect such as peeling of a resist layer used as a plating mask and a formation defect of a front surface electrode. A source pad electrode connected to a source region is formed on a front surface of a semiconductor substrate forming a vertical MOS transistor. A front surface electrode is formed on the source pad -electrode by a plating method using a resist layer having openings as a mask. The semiconductor substrate formed with the front surface electrode is thinned by back-grinding. A back surface electrode connected to a drain region is formed on the back surface of the semiconductor substrate. The front surface electrode and the back surface electrode are made of metals having the same coefficients of linear expansion, preferably copper. The front surface electrode and the back surface electrode preferably have the same thicknesses or almost the same thicknesses.

Abstract: In a power MOS transistor, for example, a source electrode is formed so as to be commonly connected to a plurality of source regions formed on the front surface. Thus, a current density varies based on in-plane resistance of the source electrode, thereby providing the necessity of increasing the number of wires connecting the sources and a lead. In the invention, an electrode structure includes a copper plating layer 10e formed on a pad electrode 10a by an electrolytic plating method, and a nickel plating layer 10f and a gold plating layer formed so as to cover the upper and side surfaces of the copper plating layer 10e by an electroless plating method.

Abstract: The invention provides a method of manufacturing a semiconductor device which achieves high reliability and high yield as well as high production efficiency. Back surface grinding (back grinding) is performed to a semiconductor substrate to thin the semiconductor substrate. A damaged layer formed by the back surface grinding is not removed at this time, and a photoresist layer is selectively formed on the back surface of the semiconductor substrate. The semiconductor substrate is then etched using the photoresist layer as a mask to form a via hole. The photoresist layer is then removed with the semiconductor substrate still placed in an etcher used in the etching process subsequently after the formation of the via hole. In this manner, the etching process and the next ashing process are performed sequentially in one apparatus.

Abstract: This invention is directed to form a homogeneous film in a via hole formed in a semiconductor device using Bosch process. The via hole that penetrates through a predetermined region in a semiconductor substrate is formed by etching the semiconductor substrate from one of its surface to the other by the Bosch process using a mask layer as a mask. Next, the mask layer is removed. Then, scallops are removed by dry etching to flatten a sidewall of the via hole. Following the above, an insulation film, a barrier layer and the like are formed homogeneously in the via hole.

Abstract: The invention is directed to a semiconductor device having a via hole and a method of manufacturing the same that achieve both the prevention of a barrier layer insufficiently covering the via hole and the control of via resistance at the same time. A semiconductor substrate having a pad electrode on its front surface is prepared. The semiconductor substrate is etched from its back surface to its front surface to form a via hole exposing the pad electrode. A first barrier layer is then formed in the via hole by a sputtering method or a PVD method and reverse-sputtering (etching). By this reverse-sputtering, the barrier layer on the bottom of the via hole is removed to expose the pad electrode. A second barrier layer is then formed on the pad electrode exposed in the via hole. The via resistance is controlled by adjusting only the thickness of the second barrier layer.

Abstract: The invention is directed to enhancement of reliability and a yield of a semiconductor device by a method of manufacturing the semiconductor device with a supporting body without making the process complex. A second insulation film, a semiconductor substrate, a first insulation film, and a passivation film are etched and removed in this order using a resist layer or a protection layer as a mask. By this etching, an adhesive layer is partially exposed in an opening. At this time, a number of semiconductor devices are separated in individual semiconductor dies. Then, as shown in FIG. 10, a solvent (e.g. alcohol or acetone) is supplied to the exposed adhesive layer through the opening to gradually reduce its adhesion and thereby a supporting body is removed from the semiconductor substrate.

Abstract: The characteristic of the semiconductor device of this invention is that the device has a piercing hole 10 formed in the semiconductor layer to touch a first metal film 18, a insulating film 12 formed on the side wall of the piercing hole 10, a second metal film 13 disposed on the first metal film 18 at the bottom of the piercing hole 10 where the insulating film 12 has not been formed and on the semiconductor layer, a barrier metal film 14 formed on the insulating film 12 in the piercing hole 10 and on the first metal film 18, and a wiring layer 15 formed inside the piercing hole 10 through the barrier metal film 14.