Abstract: A three-dimensional graphic drawing apparatus having texture pattern memory units which store a texture pattern having a set of texture pixel data designated by two-dimensional ST texture coordinate values. A display memory unit writes a two-dimensional image of a surface shape of a three-dimensional object to an address designated by two-dimensional XY display coordinate values corresponding to a display screen. Mapping units produce two-dimensional UV surface shape coordinate values of a three-dimensional object which are projected onto the two-dimensional UV surface shape. The mapping units convert the coordinate values into two-dimensional ST texture coordinate values, read out corresponding texture pixel data designating the two-dimensional XY display coordinate values corresponding to the two-dimensional UV surface shape coordinate values, and write two-dimensional XY display coordinate values into the display memory unit.

Abstract: A three-dimensional graphics drawing apparatus having a plurality of frame buffers, a Z buffer and a Z register. The frame buffers are for writing pixel data into an address designated by coordinate values (X, Y) of ZY display coordinates and for storing an image. The Z buffer is for storing a plurality of coordinate values (Z) indicating a depth direction for each pixel data written by the frame buffer. The Z register is an alternative to the Z buffer and is used for writing a single coordinate value (Z) in place of storing the coordinate value Z for every pixel in the Z buffer, when the coordinate value (Z) in the depth direction of the pixel data stored in the frame buffer have the same value for all of the pixel data. A merge unit is provided for selecting visible pixel data from the plurality of pixel data read from the frame buffer on the basis of the coordinate value (Z) in the Z buffer and the Z register. The merge unit subsequently writes the selected pixel data into a frame buffer for synthesis.

Abstract: An image processing apparatus for use in three-dimensional graphics has a frame buffer in a single device with a SAM port for simultaneously storing image information and depth information per pixel. For high speed pattern filling, the frame buffer has an image buffer for storing image information of a predetermined number of horizontal pixels in response to individual write permit signals for each pixel and a Z buffer for simultaneously outputting stored depth information and storing new depth information in response to write permit signals. A circuit identifying whether an image to be plotted is a horizontal line causes the predetermined number of pixels write permit signal output circuits to simultaneously calculate new depth information, compare the depth information read from the Z buffer with the calculated depth information and simultaneously output the write permit signals relative to the image buffer and Z buffer based on the comparison.

Abstract: A three-dimensional graphic drawing apparatus having texture pattern memory units which store a texture pattern having a set of texture pixel data designated by two-dimensional ST texture coordinate values. A display memory unit writes a two-dimensional image of a surface shape of a three-dimensional object to an address designated by two-dimensional XY display coordinate values corresponding to a display screen. Mapping units produce two-dimensional UV surface shape coordinate values of a three-dimensional object which are projected onto the two-dimensional UV surface shape. The mapping units convert the coordinate values into two-dimensional ST texture coordinate values, read out corresponding texture pixel data designating the two-dimensional XY display coordinate values corresponding to the two-dimensional UV surface shape coordinate values, and write two-dimensional XY display coordinate values into the display memory unit.

Abstract: A mode such that the same texture pattern is stored into a plurality of memories and is processed in parallel by a plurality of drawing processing units and a mode such that different texture patterns are stored into a plurality of memories and either one of the patterns is selected and processed in a time-division manner by a plurality of drawing processing units can be switched. When a pattern is enlarged and drawn at a rate of (1:N), variation values are added and the read-out coordinate values of the texture patterns are distributed, thereby making a block-like boundary inconspicuous. In the case where an underflow or overflow occurs in an adder to interpolate color values of the pixels, the well-known color value of the final pixel position is fixedly generated. In the case where the depth coordinate values of the whole picture plane which are drawn into frame buffers are equal, a single z value is written into a Z register without using a Z buffer.

Abstract: A multi-plane video RAM for displaying a color image on a display apparatus. A multi-plane bit operation unit is used for calculating input data from an external stage based on a predetermined rule corresponding to an information applied from the external stage. Memory arrays are operatively connected to the multi-plane bit operation unit for writing resultant data calculated by the multi-plane bit operation unit. Each array having three-dimensionally arranged k sets of memory planes each consisting of m (rows).times.n (columns); wherein the same corresponding positions of the k sets of memory planes are simultaneously accessed and the resultant data calculated by the multi-plane bit operation unit are also simultaneously written thereto.

Abstract: A vector pattern processing circuit for a bit map display system including a display unit having a plurality of quasi regions in a matrix form defined in a plane of the display unit each forming N.times.N dots. The circuit includes first and second memory units each including a plurality of words formed in a matrix, each word having an N.times.N bits structure; the words in the first memory unit corresponding to diagonal quasi regions of the display unit and the words in the second memory unit corresponding other diagonal quasi regions; first and second word register units, each having an N.times.N bits structure; a digital differential analyzer (DDA) generating a first dot data of a primary axis for a processing vector pattern and a second dot data of a subsidiary axis perpendicular to the primary axis in response to a gradient of the vector pattern along the primary axis for every N dots in the primary axis.