Patents by Inventor Takahiro Tanioka

Takahiro Tanioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240067883
    Abstract: Provided is a production system for producing a hydrocarbon compound, which is a hydrocarbon compound production system capable of managing an environmental load reducing effect derived from a raw material. The hydrocarbon compound production system includes a hydrogen production device that generates hydrogen, a carbon dioxide supply device that supplies a carbon dioxide, and a hydrocarbon compound production device that generates a hydrocarbon compound from each of the hydrogen generated by the hydrogen production device and the carbon dioxide supplied from the carbon dioxide supply device, wherein, on the basis of at least either one of respective environmental indicators of the hydrogen generated by the hydrogen production device and the carbon dioxide supplied from the carbon dioxide supply device, an environmental load level of the hydrocarbon compound generated by the hydrocarbon compound production device is categorized.
    Type: Application
    Filed: February 24, 2022
    Publication date: February 29, 2024
    Inventors: Shinya MARUSHIMA, Kenichi IRIE, Takahiro KAMO, Tadateru TANIOKA, Yoshimasa ANDO, Atsushi TSUTSUMI
  • Patent number: 11913684
    Abstract: A fluid circulation circuit includes a flow passage switching valve. The flow passage switching valve includes a body and a switcher. The body includes a first inlet, a second inlet, and outlets including a first outlet. The switcher is capable of switching a passage configuration to a state in which a fluid that has flowed in from the first inlet flows out of either one of the outlets and a state in which the fluid that has flowed in from the second inlet flows out of either one of the outlets.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: February 27, 2024
    Assignee: DENSO CORPORATION
    Inventors: Masamichi Makihara, Yoshiki Katoh, Takahiro Maeda, Kuniyoshi Tanioka, Akira Higuchi, Takehito Mizunuma, Takuya Hamada
  • Patent number: 7031944
    Abstract: A collection/distribution server divides processing task accepted from a customer terminal into a plurality of processing units, and transmits the units to at least one or more user terminals. The collection/distribution server receives processing results of execution on the user terminals, and integrates the processing results to send back to the customer terminal. The user terminal registers with an application server in advance for receiving a task commission from the collection/distribution server, and receives a license application from the application server. When the license application receives a processing unit from the collection/distribution server, the license application executes the processing on the user terminal. The license application sends back a result of the processing to the collection/distribution server via a network. The user terminal receives a specified service as good value for executing the processing task substituting for a contractor.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: April 18, 2006
    Assignee: NEC Corporation
    Inventor: Takahiro Tanioka
  • Publication number: 20050165974
    Abstract: A memory controller has a link monitoring circuit for detecting a communication cutoff between the memory controller and an I/O controller, and an error reply generating circuit for generating an error reply for a transaction being processed when the communication cutoff is detected. When the I/O controller is disconnected due to a fault, the memory controller, rather than the I/O controller, generates an error reply, for a transaction being processed which is addressed to an I/O device governed by the I/O controller, and sends the error reply to a processor as a source for issuing the transaction.
    Type: Application
    Filed: January 21, 2005
    Publication date: July 28, 2005
    Applicant: NEC CORPORATION
    Inventor: Takahiro Tanioka
  • Publication number: 20010049663
    Abstract: A collection/distribution server divides processing task accepted from a customer terminal into a plurality of processing units, and transmits the units to at least one or more user terminals. The collection/distribution server receives processing results of execution on the user terminals, and integrates the processing results to send back to the customer terminal.
    Type: Application
    Filed: May 15, 2001
    Publication date: December 6, 2001
    Inventor: Takahiro Tanioka
  • Patent number: 6173370
    Abstract: In a cache system which includes a single global bus (5), a plurality of central processing units (1, 2) connected to the global bus, and a main memory unit (3 or 4) connected to the global bus, each of the central processing units includes a local bus (110 or 210), a plurality of store-in-caches (101-104 or 201-204), and a bus bridge (120 or 220) connected to the local bus and the global bus for controlling, by monitoring cache tags representative of states of the store-in-caches of each central processing unit, a request delivered from one of the store-in-caches of each central processing unit to the local bus to avoid store-confliction due to the request and a different request delivered to the global bus from one of the store-in-caches of a different central processing unit of the central processing units and to thereby keepcache-coherency among the store-in-caches of the central processing units.
    Type: Grant
    Filed: June 18, 1998
    Date of Patent: January 9, 2001
    Assignee: NEC Corporation
    Inventor: Takahiro Tanioka
  • Patent number: 5809535
    Abstract: A cache memory control apparatus for a cache memory having a data memory, includes an address array, a valid bit register, a comparator, and a dual-purpose register. The dual-purpose register stores one of a valid bit and a part of an address tag. The cache memory control apparatus applies to both a standard system with a plurality of blocks-per-line and a subordinate system with one block-per-line.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: September 15, 1998
    Assignee: NEC Corporation
    Inventor: Takahiro Tanioka
  • Patent number: 5636365
    Abstract: A buffer-memory coherence control mechanism for a data processing system includes a coherence control identification device. For each entry of a second buffer memory to which a plurality of first buffer memories is connected, a control bit for coherence control is stored in a control bit table. The control bit table is provided with 1 bit corresponding to each first buffer memory and indicates which first buffer memory shares a block corresponding to the second buffer memory. When coherence control between the first buffer memories is needed, a coherence control request is issued according to the content of the control bit table only to a specified first buffer memory. In addition, even if a block was cast out of the first buffer memory, the control bit table would not be updated.
    Type: Grant
    Filed: October 5, 1994
    Date of Patent: June 3, 1997
    Assignee: NEC Corporation
    Inventor: Takahiro Tanioka