Abstract: A metal frame of an image forming apparatus includes a first support which includes a first metal plate and a second metal plate; a second support configured to support the image forming unit together with the first support; and a third support configured to connect the first support and the second support. The first metal plate includes a corner portion provided between a first portion and a second portion. The second metal plate includes a third portion, a fourth portion, and a fifth portion, wherein the fifth portion includes another corner portion located between a first stretched portion and a second stretched portion facing the corner portion of the first metal plate. A tip of the second stretched portion faces the fourth portion.

Abstract: [Object] A monitoring item selection method, device and a storage medium capable of simplifying operation and management of a system that frequently undergoes configuration changes are proposed. [Solution] Operation information concerning resources in the monitoring target device and nodes that run on the monitoring target device and make use of the resources to execute processing are periodically or randomly acquired from a monitoring target device. A relation between the nodes and a relation between the nodes and the resources based on the acquired operation information are extracted. Monitoring items of the monitoring target device are selected based on the operation information, the extracted relation between the nodes and relation between the nodes and the resources, and a pre-defined condition.

Abstract: A method for performing test site synchronization within automated test equipment (ATE) is presented. The method comprises controlling a plurality of test program controllers (TPCs) using a plurality of bridge controllers (BCs), wherein each TPC can initiate multiple asynchronous events. For an asynchronous event initiated by a TPC, raising a busy flag while the asynchronous event is not yet complete and de-asserting the busy flag when the asynchronous event is complete, wherein the asynchronous event corresponds to a task requiring an indeterminate amount of time. It also comprises generating a busy signal in the first BCs in response to receiving a busy flag from any of the plurality of TPCs, wherein the busy signal remains asserted while any of the plurality of TPCs asserts a busy flag. Finally, it comprises transmitting the busy signal to the plurality of TPCs, wherein the TPCs use the busy signal to synchronize operations.

Abstract: [Object] A monitoring item selection method, device and a storage medium capable of simplifying operation and management of a system that frequently undergoes configuration changes are proposed. [Solution] Operation information concerning resources in the monitoring target device and nodes that run on the monitoring target device and make use of the resources to execute processing are periodically or randomly acquired from a monitoring target device. A relation between the nodes and a relation between the nodes and the resources based on the acquired operation information are extracted. Monitoring items of the monitoring target device are selected based on the operation information, the extracted relation between the nodes and relation between the nodes and the resources, and a pre-defined condition.

Abstract: A method for performing test site synchronization within automated test equipment (ATE) is presented. The method comprises controlling a plurality of test program controllers (TPCs) using a plurality of bridge controllers (BCs), wherein each TPC can initiate multiple asynchronous events. For an asynchronous event initiated by a TPC, raising a busy flag while the asynchronous event is not yet complete and de-asserting the busy flag when the asynchronous event is complete, wherein the asynchronous event corresponds to a task requiring an indeterminate amount of time. It also comprises generating a busy signal in the first BCs in response to receiving a busy flag from any of the plurality of TPCs, wherein the busy signal remains asserted while any of the plurality of TPCs asserts a busy flag. Finally, it comprises transmitting the busy signal to the plurality of TPCs, wherein the TPCs use the busy signal to synchronize operations.

Abstract: An address signal generating circuit generates an address signal which designates the address in memory to be accessed. An inversion inhibition signal generating unit generates multiple patterns of inversion inhibition signals each having the same bit width as that of the address signal, and each having a function of preventing particular bits of the address signal from being inverted. A selector selects one of the multiple patterns of inversion inhibition signals generated by the inversion inhibition signal generating unit, and outputs the inversion inhibition signal thus selected. When an inversion control signal is asserted, an address signal inverting circuit inverts only the bits of the address signal which are not prevented from being inverted according to the inversion inhibition signal selected by the selector, and outputs the resulting address signal.

Abstract: A test apparatus testing a device under test includes a main pattern generating section that generates a main pattern, a plurality of sub-pattern generating sections each of which generates a sub-pattern corresponding to a different one of segment cycles based on a main pattern, the segment cycles formed by dividing a test cycle period, a test signal supplying section that supplies, to the device under test, a multiplexed test pattern formed by switching sub-patterns generated by the plurality of sub-pattern generating sections at each of the segment cycles, and a plurality of delay selecting sections each of which selects one of a main pattern that is from the main pattern generating section and a delayed main pattern that is formed by delaying the main pattern from the main pattern generating section by a test cycle, to supply the selected one to the corresponding sub-pattern generating section.

Abstract: An address operation circuit generates a row address which indicates an address in memory under test to be accessed. The row address memory stores the row addresses generated by the address operation circuit in increments of banks. A memory control signal that includes a bank address to be applied to the memory under test, and which is generated according to a pattern program, is used as a save address to be used to write the row address to the row address memory, and as a load address to be used to read out the row address from the row address memory.

Abstract: An address signal generating circuit generates an address signal which designates the address in memory to be accessed. An inversion inhibition signal generating unit generates multiple patterns of inversion inhibition signals each having the same bit width as that of the address signal, and each having a function of preventing particular bits of the address signal from being inverted. A selector selects one of the multiple patterns of inversion inhibition signals generated by the inversion inhibition signal generating unit, and outputs the inversion inhibition signal thus selected. When an inversion control signal is asserted, an address signal inverting circuit inverts only the bits of the address signal which are not prevented from being inverted according to the inversion inhibition signal selected by the selector, and outputs the resulting address signal.

Abstract: An address operation circuit generates a row address which indicates an address in memory under test to be accessed. The row address memory stores the row addresses generated by the address operation circuit in increments of banks. A memory control signal that includes a bank address to be applied to the memory under test, and which is generated according to a pattern program, is used as a save address to be used to write the row address to the row address memory, and as a load address to be used to read out the row address from the row address memory.

Abstract: A test apparatus testing a device under test includes a main pattern generating section that generates a main pattern, a plurality of sub-pattern generating sections each of which generates a sub-pattern corresponding to a different one of segment cycles based on a main pattern, the segment cycles formed by dividing a test cycle period, a test signal supplying section that supplies, to the device under test, a multiplexed test pattern formed by switching sub-patterns generated by the plurality of sub-pattern generating sections at each of the segment cycles, and a plurality of delay selecting sections each of which selects one of a main pattern that is from the main pattern generating section and a delayed main pattern that is formed by delaying the main pattern from the main pattern generating section by a test cycle, to supply the selected one to the corresponding sub-pattern generating section.

Abstract: A power control apparatus includes a latch relay interposed between a power source and electronic control units, and a control section changed into an operative state when connected to the power source upon closure of a first switch, and supplies a drive current to a reset coil of the latch relay, thereby disconnecting power supply from the power source to the control units, when second switches are operated in a predetermined operation pattern.

Abstract: There are provided a failure repair analyzing and processing method and a memory testing apparatus provided with a failure repair analyzing and processing apparatus using this method, that are capable of reducing a time duration required to perform the failure repair analysis and processing for a multi-bit memory having redundancy structure. A plurality of repair analysis units as well as a common failure analysis memory are provided, and these repair analysis units are concurrently operated in parallel with each other, thereby to carry out respective repair analyses and processings for failure memory cells of plural data bits read out from the failure analysis memory in the plural repair analysis units concurrently and in parallel with each other. As a result, a time duration required to execute the failure repair analysis and processing is shortened.

Abstract: A power control apparatus includes a latch relay interposed between a power source and electronic control units, and a control section changed into an operative state when connected to the power source upon closure of a first switch, and supplies a drive current to a reset coil of the latch relay, thereby disconnecting power supply from the power source to the control units, when second switches are operated in a predetermined operation pattern.

Abstract: A method and apparatus for analyzing repair of failure cells in a memory are capable of detecting an address of a failure memory cell in a short time. The memory testing apparatus includes a failure relief analyzer for testing a memory having a plurality of storage areas, counting the number of failure memory cells for each storage area, and reading out the counted number of failure memory cells. The apparatus has an analyzed storage area detector for searching whether a failure memory cell exists and determining whether a failure relief analysis should be performed, a failure line searching apparatus for searching row addresses to detect whether a failure memory cell exists, and an address scanning apparatus whose operation is started when the failure line searching apparatus detects the presence of a failure memory cell, and for detecting a column address in the direction orthogonal to the row address line on which the detected failure memory cell exists.

Abstract: There are provided a failure repair analyzing and processing method and a memory testing apparatus provided with a failure repair analyzing and processing apparatus using this method, that are capable of reducing a time duration required to perform the failure repair analysis and processing for a multi-bit memory having redundancy structure. A plurality of repair analysis units as well as a common failure analysis memory are provided, and these repair analysis units are concurrently operated in parallel with each other, thereby to carry out respective repair analyses and processings for failure memory cells of plural data bits read out from the failure analysis memory in the plural repair analysis units concurrently and in parallel with each other. As a result, a time duration required to execute the failure repair analysis and processing is shortened.

Abstract: A method of analyzing a repair of failure memory cell in a memory is provided, which is capable of searching a must-repair of a memory at high speed and of performing a simulation process for relieving a must-repair at high speed at the time point when it has been detected. There are provided a row address failure number counter/memory for counting the number of failure memory cells on each row address in the row address direction and storing it and a column address failure number counter/memory for counting the number of failure memory cells on each column address in the column address direction and storing it. The stored value in either one counter/memory is read out and the number of failure memory cells on each address is compared with the number of spare lines.

Abstract: There is provided a memory testing apparatus provided with a failure relief analyzer, which need not initialize, prior to counting the number of failure data, failure storing memories for storing therein counted values of the number of failure data. An output altering circuit is constituted by an initialization controller 7 for outputting an initialization signal on the basis of a row failure counter address signal outputted from an RFC address formatter 33 and a column failure counter address signal outputted from a CFC address formatter 43, and data controllers 34, 44 and 84 to each of which an initialization signal outputted from the initialization controller 7 is applied. By use of the output altering circuit, respective values of data read out from each address of a row failure storing memory, each address of a column failure storing memory and each address of a total failure storing memory are outputted as “0” only when they are read out at the first time.