Abstract: Provided is a plasma processing method performed with a plasma processing apparatus including a chamber. The method includes: (a) preparing a substrate on a substrate support in the chamber, the substrate including an etching target film and a metal-containing film disposed on the etching target film, the metal-containing film including a side face defining at least one opening on the etching target film; (b) forming a deposited film on at least a portion of the surface of the metal-containing film using a plasma formed from a first processing gas, the first processing gas including a gas containing silicon, carbon or metal; and (c) removing at least a portion of the side face of the metal-containing film using a plasma formed from a second processing gas.

Abstract: A plasma processing method according to the present disclosure is performed with a plasma processing apparatus, and includes: (a) preparing a substrate on a substrate support in the chamber, the substrate having an etching target film including a first silicon-containing film, and a first metal-containing film on the etching target film, the first metal-containing film including an opening pattern; and (b) etching the etching target film. (b) includes supplying a processing gas including one or more gases containing carbon, hydrogen, and fluorine into the chamber to form a plasma from the processing gas within the chamber and etch the first silicon-containing film to form the opening pattern in the first silicon-containing film, and a ratio of the number of hydrogen atoms to the number of fluorine atoms in the processing gas is 0.3 or more.

Abstract: A plasma processing method includes: providing a substrate including a silicon-containing film and a mask film having an opening pattern, on a substrate support; and etching the silicon-containing film using the mask film as a mask, with a plasma generated by a plasma generator provided in the chamber. The etching includes: supplying a processing gas containing one or more gases including carbon, hydrogen, and fluorine into the chamber; generating a plasma from the processing gas by supplying a source RF signal to the plasma generator; and supplying a bias RF signal to the substrate support unit. In the etching, the silicon-containing film is etched by at least hydrogen fluoride generated from the processing gas, while forming a carbon-containing film on at least a part of a surface of the mask film.

Abstract: In one exemplary embodiment, a method for forming a pattern includes (a) forming, on a substrate, a first pattern having an opening and containing a first material, (b) forming a filling portion in the opening, the filling portion containing a second material different from the first material, and (c) removing the first pattern so that the filling portion remains as a second pattern inverted with respect to the first pattern. At least one of the first material or the second material contains tin.

Abstract: A plasma processing method includes: providing a substrate including: (a) an etching target film; (b) a photoresist film on an upper surface of the etching target film, having a side surface that defines at least one opening in the upper surface of the etching target film; and (c) a first film including a first portion on an upper surface of the photoresist film and second portion on the side surface of the photoresist film, the first portion having a film thickness larger than that of the second portion; and trimming at least a part of the side surface of the photoresist film and at least a part of the second portion of the first film.

Abstract: A delay measuring circuit includes a first trigger-signal generating unit that, when a value of a signal input to a circuit under test, changes, generates a first trigger signal. The delay measuring circuit includes a second trigger-signal generating unit that, when a value of a signal output from the circuit under test changes, generates a second trigger signal. The delay measuring circuit includes a delay unit that includes a plurality of delay elements connected in series. The delay measuring circuit includes a delay information retaining unit that individually captures and retains the first trigger signal output from each of the delay elements included in the delay unit between when the first trigger signal is generated by the first trigger-signal generating unit and when the second trigger signal is generated by the second trigger-signal generating unit.

Abstract: A delay measuring circuit includes a first trigger-signal generating unit that, when a value of a signal input to a circuit under test, changes, generates a first trigger signal. The delay measuring circuit includes a second trigger-signal generating unit that, when a value of a signal output from the circuit under test changes, generates a second trigger signal. The delay measuring circuit includes a delay unit that includes a plurality of delay elements connected in series. The delay measuring circuit includes a delay information retaining unit that individually captures and retains the first trigger signal output from each of the delay elements included in the delay unit between when the first trigger signal is generated by the first trigger-signal generating unit and when the second trigger signal is generated by the second trigger-signal generating unit.

Abstract: In an electronic component mounting apparatus, a vertical load and horizontal loads applied to an electronic component are detected by a load sensor that has piezoelectric elements provided in a stack in a mounting direction of the electronic component. Therefore, a size in a horizontal direction of the load sensor can be reduced, and a load applied to the electronic component can be detected at a neighborhood of a mounting position of the electronic component. Moreover, by comparing a position, in a two-dimensional space in which load values in an X-direction and Y-direction of the horizontal load serve as coordinate values, with a tolerance range in the two-dimensional space, a mounting failure can be detected from a deviation in the horizontal loads.

Abstract: A method of forming a bump electrode on an IC electrode includes the steps of forming a ball bond on an IC electrode by a wire bonding apparatus, moving a bonding capillary upward, moving the bonding capillary sideways and then downward, bonding an Au wire to the ball bond portion, and cutting the Au wire. The Au wire is prevented from coming in contact with portions around the ball bond portion other than the ball bond portion by presetting a descent position of the bonding capillary to a position higher than a position in which the ball bond is formed.

Abstract: A method of forming a bump electrode on an IC electrode includes the steps of forming a ball bond on an IC electrode by a wire bonding apparatus, moving a bonding capillary upward, moving the bonding capillary sideways and then downward, bonding an Au wire to the ball bond portion, and cutting the Au wire. The Au wire is prevented from coming in contact with portions around the ball bond portion other than the ball bond portion by presetting a descent position of the bonding capillary to a position higher than a position in which the ball bond is formed.

Abstract: In a bump bonding technique for forming a bump on an IC, including forming a ball at the tip of a gold wire protruding from a capillary, and providing a metal-to-metal joint by applying ultrasonic vibration from a ultrasonic head through the capillary while pressing the ball against a pad portion on the IC, the metal-to-metal joint is provided by applying the ultrasonic vibration at a frequency in a range of 130 to 320 kHz, more preferably in a range of 170 to 270 kHz, and most preferably at a frequency of 230±10 kHz at room temperatures and atmospheric pressure. Consequently, a bump is formed on an IC having a low heat resistance temperature in a satisfactory joint condition, and a bump is formed with good positional accuracy without giving the influence of heat to the surroundings.

Abstract: A method of forming a bump electrode on an IC electrode includes the steps of forming a ball bond on an IC electrode by a wire bonding apparatus, moving a bonding capillary upward, moving the bonding capillary sideways and then downward, bonding an Au wire to the ball bond portion, and cutting the Au wire. The Au wire is prevented from coming in contact with portions around the ball bond portion other than the ball bond portion by presetting a descent position of the bonding capillary to a position higher than a position in which the ball bond is formed.

Abstract: In the electronic component mounting apparatus, a vertical load and horizontal loads applied to an electronic component are detected by a load sensor that have piezoelectric elements provided in a stack in the mounting direction of the electronic component. Therefore, the size in the horizontal direction of the load sensor can be reduced, and the load applied to the electronic component can be detected at the neighborhood of the mounting position of the electronic component. Moreover, by comparing a position in a two-dimensional space in which the load values in the X-direction and the Y-direction of the horizontal load are served as coordinate values with a tolerance range in the two-dimensional space, mounting failure can be detected from a deviation in the horizontal loads.

Abstract: A carrier tool having a protective ring with a sheet extended over an underside of the ring is used, a semiconductor wafer is made to adhere to the sheet, the semiconductor wafer, being surrounded by the protective ring, is carried from a container device to a bonding stage. Bonding is performed on the bonding stage, and the wafer is carried out to another container device, consequently damage of the wafer is avoided.

Abstract: A bare chip mounting method includes: a dicing step for dividing a semiconductor wafer into individual IC chips while the semiconductor wafer is being attached to a carrier; a washing step for washing the diced semiconductor wafer; a bump-bonding for carrying the washed semiconductor wafer to an assembly process while the semiconductor wafer is being attached to the carrier so as to form a bump on an electrode pad of the wafer; and a mounting step for mounting each of the IC chips, on which the bump is formed, onto a circuit formation body.

Abstract: To provide a film substrate treatment apparatus that appropriately mounts film substrates on an electrostatic adsorption stage. In the film substrate treatment apparatus, adsorption pads are disposed on the first adsorption units that mount film substrates on an electrostatic stage, and a pressing member that presses the edge portion areas of the film substrates against the stage is provided. The film substrates can thereby be reliably attached to the stage, and the film substrates can be appropriately treated in a decompressed atmosphere.

Abstract: To provide a film substrate treatment apparatus that appropriately mounts film substrates on an electrostatic adsorption stage. In the film substrate treatment apparatus, adsorption pads are disposed on the first adsorption units that mount film substrates on an electrostatic stage, and a pressing member that presses the edge portion areas of the film substrates against the stage is provided. The film substrates can thereby be reliably attached to the stage, and the film substrates can be appropriately treated in a decompressed atmosphere.

Abstract: Provided is a construction including a stage having a suction hole for sucking an electronic component and fixing the same in position and position regulating suction hole for sucking an electronic component when the electronic component is regulated in position, a position regulating pawl for positioning the electronic component on the stage and a position regulating suction force control section capable of controlling a position regulating suction force when the electronic component is regulated in position on the stage.

Abstract: In a bump bonding technique for forming a bump on an IC, including forming a ball at the tip of a gold wire protruding from a capillary, and providing a metal-to-metal joint by applying ultrasonic vibration from a ultrasonic head through the capillary while pressing the ball against a pad portion on the IC, the metal-to-metal joint is provided by applying the ultrasonic vibration at a frequency in a range of 130 to 320 kHz, more preferably in a range of 170 to 270 kHz, and most preferably at a frequency of 230±10 kHz at room temperatures and atmospheric pressure. Consequently, a bump is formed on an IC having a low heat resistance temperature in a satisfactory joint condition, and a bump is formed with good positional accuracy without giving the influence of heat to the surroundings.

Abstract: A bare chip mounting method includes: a dicing step for dividing a semiconductor wafer into individual IC chips while the semiconductor wafer is being attached to a carrier; a washing step for washing the diced semiconductor wafer; a bump-bonding for carrying the washed semiconductor wafer to an assembly process while the semiconductor wafer is being attached to the carrier so as to form a bump on an electrode pad of the wafer; and a mounting step for mounting each of the IC chips, on which the bump is formed, onto a circuit formation body.