Abstract: A method of manufacturing a silicon carbide semiconductor device, including forming a first-conductivity-type region in a SiC semiconductor substrate, selectively forming a plurality of second-conductivity-type regions in the first-conductivity-type region, forming an interlayer insulating film covering the first-conductivity-type region and the second-conductivity-type regions, selectively removing the interlayer insulating film to form a plurality of openings exposing the second-conductivity-type regions, forming, in each opening, a layered metal film having a cap film stacked on an aluminum film, thermally diffusing aluminum atoms in the aluminum film to thereby form a plurality of second-conductivity-type high-concentration regions, removing the layered metal film, selectively removing the interlayer insulating film to form a contact hole, forming a first electrode by sequentially stacking a titanium film and a metal film containing aluminum on the first surface of the semiconductor substrate in the conta

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In n?-type drift layer, an n-type region, a lower second p+-type region and a first p+-type region are provided. A part of the lower second p+-type region extends in a direction opposite that of a depth of the trench and is connected to the p-type base layer.

Abstract: In a method of manufacturing a silicon carbide semiconductor device that is a silicon carbide diode having a JBS structure including a mixture of a Schottky junction and a pn junction and that maintains low forward voltage through a SBD structure and enhances surge current capability, nickel silicide films are formed in an oxide film by self-alignment by causing a semiconductor substrate and a metal material film to react with one another through two sessions of heat treatment including a low-temperature heat treatment and a high-temperature heat treatment, the metal material film including sequentially a first nickel film, an aluminum film, and a second nickel film, the first nickel film being in contact with an entire area of a connecting region of a FLR and p-type regions respectively exposed in openings of the oxide film.

Abstract: A semiconductor device having, in a plan view, a termination region surrounding an active region. The semiconductor device includes a semiconductor substrate containing silicon carbide, a first-conductivity-type region provided in the semiconductor substrate at its first main surface, a plurality of first second-conductivity-type regions selectively formed in the semiconductor substrate at its first main surface, a plurality of silicide films respectively in ohmic contact with the first second-conductivity-type regions, a first electrode that is in contact with the silicide films to form ohmic regions, with the first second-conductivity-type regions to form non-operating regions, and with the first-conductivity-type region to form Schottky regions, a second electrode provided at a second main surface of the semiconductor substrate, and a second second-conductivity-type region provided in the termination region.

Abstract: A semiconductor device including a silicon carbide semiconductor substrate having a first-conductivity-type region at its first main surface. The semiconductor device has, at the first main surface, a plurality of first second-conductivity-type regions and a second second-conductivity-type region selectively provided in the first-conductivity-type region, respectively in an active region and a connecting region of the semiconductor device, and an oxide film provided in a termination region of the semiconductor device and having an inner end that faces the active region. A first silicide film is in ohmic contact with the first second-conductivity-type regions. A second silicide film is in contact with the inner end of the oxide film and in ohmic contact with the second second-conductivity-type region. The semiconductor device has a first electrode including a titanium film and a metal electrode film stacked sequentially on the first main surface, and a second electrode provided at a second main surface.

Abstract: A method of manufacturing a silicon carbide semiconductor device, including forming a first-conductivity-type region in a SiC semiconductor substrate, selectively forming a plurality of second-conductivity-type regions in the first-conductivity-type region, forming an interlayer insulating film covering the first-conductivity-type region and the second-conductivity-type regions, selectively removing the interlayer insulating film to form a plurality of openings exposing the second-conductivity-type regions, forming, in each opening, a layered metal film having a cap film stacked on an aluminum film, thermally diffusing aluminum atoms in the aluminum film to thereby form a plurality of second-conductivity-type high-concentration regions, removing the layered metal film, selectively removing the interlayer insulating film to form a contact hole, forming a first electrode by sequentially stacking a titanium film and a metal film containing aluminum on the first surface of the semiconductor substrate in the conta

Abstract: In a method of manufacturing a silicon carbide semiconductor device that is a silicon carbide diode having a JBS structure including a mixture of a Schottky junction and a pn junction and that maintains low forward voltage through a SBD structure and enhances surge current capability, nickel silicide films are formed in an oxide film by self-alignment by causing a semiconductor substrate and a metal material film to react with one another through two sessions of heat treatment including a low-temperature heat treatment and a high-temperature heat treatment, the metal material film including sequentially a first nickel film, an aluminum film, and a second nickel film, the first nickel film being in contact with an entire area of a connecting region of a FLR and p-type regions respectively exposed in openings of the oxide film.

Abstract: A semiconductor device having, in a plan view, a termination region surrounding an active region. The semiconductor device includes a semiconductor substrate containing silicon carbide, a first-conductivity-type region provided in the semiconductor substrate at its first main surface, a plurality of first second-conductivity-type regions selectively formed in the semiconductor substrate at its first main surface, a plurality of silicide films respectively in ohmic contact with the first second-conductivity-type regions, a first electrode that is in contact with the silicide films to form ohmic regions, with the first second-conductivity-type regions to form non-operating regions, and with the first-conductivity-type region to form Schottky regions, a second electrode provided at a second main surface of the semiconductor substrate, and a second second-conductivity-type region provided in the termination region.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In n?-type drift layer, an n-type region, a lower second p+-type region and a first p+-type region are provided. A part of the lower second p+-type region extends in a direction opposite that of a depth of the trench and is connected to the p-type base layer.

Abstract: A semiconductor device including a silicon carbide semiconductor substrate having a first-conductivity-type region at its first main surface. The semiconductor device has, at the first main surface, a plurality of first second-conductivity-type regions and a second second-conductivity-type region selectively provided in the first-conductivity-type region, respectively in an active region and a connecting region of the semiconductor device, and an oxide film provided in a termination region of the semiconductor device and having an inner end that faces the active region. A first silicide film is in ohmic contact with the first second-conductivity-type regions. A second silicide film is in contact with the inner end of the oxide film and in ohmic contact with the second second-conductivity-type region. The semiconductor device has a first electrode including a titanium film and a metal electrode film stacked sequentially on the first main surface, and a second electrode provided at a second main surface.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In n?-type drift layer, an n-type region, a lower second p+-type region and a first p+-type region are provided. A part of the lower second p+-type region extending in a direction opposite that of a depth of the trench and connected to the p-type base layer.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, an upper second p+-type region, a lower second p+-type region and a first p+-type region are provided. The lower second p+-type region is provided orthogonal to a trench, and a total mathematical area regions that are between the first p+-type region and the p-type base layer and that include the n-type region is at least two times a total mathematical area of regions that are between the first p+-type region and the p-type base layer and that include the upper second p+-type region.

Abstract: On a surface of an n-type silicon carbide epitaxial layer on an n+-type silicon carbide substrate, first and second p+-type base regions are formed in the n-type silicon carbide epitaxial layer, an n-type region is formed in the n-type silicon carbide epitaxial layer, a p-type base layer is formed on the n-type region, an n+-type source region and a p++-type contact region are formed in the p-type base layer, and a trench is formed to a position shallower than the second p+-type base region and penetrates the p-type base layer. A first sidewall angle of the trench at a position of the p-type base layer is 80° to 90° with respect to a main surface. A difference of the first sidewall angle and a second sidewall angle of the trench at a position deeper than a boundary of the p-type base layer and the n-type region is 1° to 25°.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the p-type base layer, an n+-type source region is provided. A trench that penetrates the p-type base layer and the n+-type source region, and reaches the n?-type drift layer is provided. The first p+-type region is in contact with a bottom of the trench and is implanted with an impurity that determines a conductivity type of the first p+-type region and a first element that bonds with a second element that is displaced by the impurity, the impurity and the second element being implanted at a predetermined ratio.

Abstract: On a front surface of a semiconductor base, an n?-type drift layer, a p-type base layer, an n++-type source region, and a gate trench and a contact trench penetrating the n++-type source region and the p-type base layer and reaching the n?-type drift layer are provided. The contact trench is provided separated from the gate trench. A Schottky metal is embedded in the contact trench and forms a Schottky contact with the n?-type drift layer at a side wall of the contact trench. An ohmic metal is provided at a bottom of the contact trench and forms an ohmic contact with the n?-type drift layer.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In n?-type drift layer, an n-type region, a lower second p+-type region and a first p+-type region are provided. A part of the lower second p+-type region extending in a direction opposite that of a depth of the trench and connected to the p-type base layer.

Abstract: A vertical MOSFET of a trench gate structure includes an n?-type drift layer and a p+-type base layer formed by epitaxial growth. The vertical MOSFET includes a trench that penetrates the n?-type drift layer and the p+-type base layer. A low-concentration thin film is provided in the trench. The low-concentration thin film is in contact with the p+-type base layer and is of the same conductivity type as the p+-type base layer. Further, the low-concentration thin film has an impurity concentration that is lower than that of the p+-type base layer.

Abstract: A silicon carbide semiconductor device has an n+-type drift layer provided on a front surface of an n+-type silicon carbide substrate, a first p+-type region provided in a surface layer of the n+-type drift layer, and a trench formed on a front surface side of the n+-type silicon carbide substrate. The first p+-type region is constituted by a deep first p+-type region at a position deeper than a bottom of the trench, and a shallow first p+-type region at position shallower than the bottom of the trench. The deep first p+-type region is implanted with a first element at a predetermined ratio, the first element bonding with a second element that is displaced by an impurity that determines a conductivity type of the first p+-type region.

Abstract: A semiconductor device includes an n-type silicon carbide epitaxial layer formed on an n+-type silicon carbide semiconductor substrate, p+-type base regions formed in the n-type silicon carbide epitaxial layer, a dense n-type region formed in the n-type silicon carbide epitaxial layer, a p-type base layer formed on the dense n-type region, an n+-type source region and a p++-type contact region formed in the p-type base layer, a trench penetrating the p-type base layer in a depth direction of a part of one of the p+-type base regions, and a gate electrode formed on a gate insulating film in the trench. The n+-type source region is formed using two dopant types, phosphorus and carbon. A dose amount DC of carbon satisfies 0.7?DC/Dp?1.3 with respect to a dose amount Dp of phosphorus. An impurity concentration of the n+-type source region ranges from 1018 to 1021.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, an upper second p+-type region, a lower second p+-type region and a first p+-type region are provided. The lower second p+-type region is provided orthogonal to a trench, and a total mathematical area regions that are between the first p+-type region and the p-type base layer and that include the n-type region is at least two times a total mathematical area of regions that are between the first p+-type region and the p-type base layer and that include the upper second p+-type region.