Patents by Inventor Takaji Ohtsu
Takaji Ohtsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 4591916Abstract: A solid state image pickup device comprises first switching elements (S'.sub.11 to S'.sub.mn) arrayed in horizontal and vertical rows and composed of a plurality of P-channel insulated-gate field-effect transistors, the first switching elements in each vertical row having one terminals connected in common, a photoelectric transducer layer (17) disposed over the horizontal and vertical rows of the first switching elements (S'.sub.11 to S'.sub.mn) and electrically connected to other terminals of the first switching elements (S'.sub.11 to S'.sub.mn), and a plurality of second switching elements (T.sub.1 to T.sub.n) disposed respectively for the vertical rows of the first switching elements (S'.sub.11 to S'.sub.mn) and connected respectively to the one terminals connected in common of the first switching elements in the respective vertical rows, with the arrangement thereof wherein the horizontal rows of the first switching elements (S'.sub.11 to S'.sub.Type: GrantFiled: November 25, 1983Date of Patent: May 27, 1986Assignee: Sony CorporationInventors: Mitsuo Soneda, Toshikazu Maekawa, Takaji Ohtsu
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Patent number: 4584608Abstract: A solid state image pickup device comprises a plurality of image pickup picture units (E.sub.11 to E.sub.mn) arrayed in horizontal and vertical rows and composed of first switching elements (S.sub.11 to S.sub.mn) and photoelectric transducers (D.sub.11 to D.sub.mn : 24) electrically connected to the first switching elements (S.sub.11 to S.sub.mn), and a plurality of second switching elements (T'.sub.1 to T'.sub.n) connected in common to the respective vertical rows of the first switching elements (S.sub.11 to S.sub.mn) in the image pickup picture units (E.sub.11 to E.sub.mn) and each composed of a depletion-mode insulated-gate field-effect transistors. The horizontal rows of the first switching elements (S.sub.11 to S.sub.mn) in the image pickup picture units (E.sub.11 to E.sub.mn) are selectively energizable and the second switching elements (T'.sub.1 to T'.sub.n) are also selectively energizable to deliver signals based on signal charge generated by the photoelectric transducers (D.sub.11 to D.sub.Type: GrantFiled: December 5, 1983Date of Patent: April 22, 1986Assignee: Sony CorporationInventors: Mitsuo Soneda, Toshikazu Maekawa, Takaji Ohtsu
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Patent number: 4578597Abstract: A pulse generating circuit comprises a first series connection of a first switching element (3:13) and a second switching element (4), a second series connection of a capacitive element (5) and a third switching element (6) coupled with a connecting point between the first and second switching elements, an amplifying element (7) having input and output terminals connected to both ends of the capacitive element (5), respectively, and a fourth switching element (8) connected to the output end of the amplifying element (7), and is supplied with a first input signal varying in level through the control terminals of the first and third switching elements (3:13, 6) and a second input signal varying in level through the control terminals of the second and fourth switching elements (4, 8), thereby to obtain a pulse having the width corresponding to the time interval from a variation in the level of the first input signal to a variation in the level of the second input signal at the output end of the amplifying elemenType: GrantFiled: November 2, 1983Date of Patent: March 25, 1986Assignee: Sony CorporationInventors: Mitsuo Soneda, Manami Fukuzawa, Takaji Ohtsu
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Patent number: 4485380Abstract: A liquid crystal matrix display device has a plurality of liquid crystal display elements arranged in an X-Y matrix pattern. Vertical transmitting lines are connected to all of the display elements of each column, and horizontal transmitting lines are connected to each of the display elements of each row. Each of the vertical lines is connected through an input switching element to an input circuit to receive a video input signal and a horizontal pulse generator provides sequential pulse signals to control terminals of the input switching elements. In order to compensate for crosstalk that occurs because of parasitic capacitance between the vertical transmitting lines and the liquid crystal display elements, auxiliary lines are provided for the columns of such display elements, and each has a predetermined compensating capacitance relative to its associated liquid crystal display elements.Type: GrantFiled: June 8, 1982Date of Patent: November 27, 1984Assignee: Sony CorporationInventors: Mitsuo Soneda, Takaji Ohtsu, Ken Kutaragi
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Patent number: 4466018Abstract: Solid-state image pickup apparatus, such as an MOS imager, has a two-dimensional array of picture element units each formed of a photo sensitive element and a gating element. The picture unit elements discharge a signal charge onto vertical and horizontal transmitting lines in response to vertical and horizontal scanning pulses. Then, a resulting signal current is used to develop an output video signal. In order to give the output video signal a good S/N ratio, a gain-controlled current amplifier is employed. In several embodiments, the gain-controlled amplifier includes first through fourth transistors with the base-emitter junctions of the first and second transistors and of the third and fourth transistors connected in series, with a constant current source coupled to the first transistor, controlled current sources connected to the second and third transistors, and a load device coupled to the fourth transistor.Type: GrantFiled: May 19, 1982Date of Patent: August 14, 1984Assignee: Sony CorporationInventors: Mitsuo Soneda, Takashi Noguchi, Takaji Ohtsu
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Patent number: 4463383Abstract: Solid-state image pickup apparatus, such as an MOS imager, has a two-dimensional array of picture element units each formed of a photo sensitive element and a gating element, and scanning circuits for supplying horizontal and vertical scanning pulses. The picture unit elements in turn discharge a signal charge onto vertical and horizontal transmitting lines in response to the vertical and horizontal scanning pulses. Then, a resulting signal current is used to develop an output video signal. In order to provide a strong output video signal with a good S/N ratio, a current mirror circuit, formed of an input transistor and an output transistor with first current-carrying electrodes joined together to a voltage reference point and with control electrodes joined together, amplifies the signal current. A second current-carrying electrode of the input transistor receives a constant current from a current source and also receives the signal current.Type: GrantFiled: May 5, 1982Date of Patent: July 31, 1984Assignee: Sony CorporationInventors: Mitsuo Soneda, Takashi Noguchi, Takaji Ohtsu
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Patent number: 4447812Abstract: A liquid crystal matrix display device has a plurality of display elements arranged in an X-Y matrix pattern. Vertical transmitting lines are connected to all of the display elements of each column, and horizontal transmitting lines are connected to each of the display elements of each row. Each of the vertical lines is connected through an input switching element to an input circuit to receive a video input signal and a horizontal pulse generator provides sequential pulse signals to control terminals of the input switching elements. In order to improve the resolution without sacrifice of contrast, the vertical transmitting lines are arranged into groups of a predetermined number of such lines, and the input switching elements associated with the lines of each such group have their control electrodes coupled together to a respective output of the horizontal scanning pulse generator.Type: GrantFiled: June 3, 1982Date of Patent: May 8, 1984Assignee: Sony CorporationInventors: Mitsuo Soneda, Takaji Ohtsu
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Patent number: 4101921Abstract: In a memory type insulated gate field effect semiconductor device including a semiconductor layer of one conductivity type, a source region of the opposite conductivity type formed in the surface of the semiconductor layer, a drain region of the opposite conductivity type formed in the surface of the semiconductor layer, a gate insulating layer affixed to the surface of the semiconductor layer, and a gate electrode deposited on the surface of the gate insulating layer, the gate insulating layer has a pair of thick gate guarding portions which exist on side of the source and drain regions, and a thin memory portion intermediate between the thick gate guarding portions, and a surface impurity concentration per square centimeter of the semiconductor layer under the thick gate guarding portions is different from a surface impurity concentration per square centimeter of the semiconductor layer under the tin memory portion.Type: GrantFiled: February 25, 1977Date of Patent: July 18, 1978Assignee: Sony CorporationInventors: Takashi Shimada, Kenichi Inoue, Takaji Ohtsu, Hidenobu Mochizuki, Jiro Yamaguchi