Patents by Inventor Takako Murakami

Takako Murakami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Helium injected footwear with adjustable shoe size upper and adjustable firmness sole
    Patent number: 7380351
    Abstract: An improved sole and upper for use with all types of footwear which provides adjustable shoe sizing, adjustable sole firmness for differing activities, allows the wearer to view and touch the technology contained in the footwear, while aiding in the facilitation of exercise and healthful movement, according to the use of the footwear for the purpose of comfortable standing, pleasurable walking, steadier running, safer cross-training, while adding extra comfort for the foot during all activities.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: June 3, 2008
    Inventors: Luigi Alessio Pavone, Lori Takako Murakami
  • Manufacturing method and apparatus of a semiconductor integrated circuit device
    Patent number: 6035111
    Abstract: According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: March 7, 2000
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Rieko Suzuki, Kiyoshi Saida, Kazushige Itazu, Eiji Fujine, Yoshihiro Kamiya, Yoshitaka Uchida, Takako Murakami, Teruhisa Tsuyuki, Kazunori Kawazoe, Takeshi Shimazaki, Yukimi Nishiwaki
  • Manufacturing method and apparatus of a semiconductor integrated circuit device
    Patent number: 5618744
    Abstract: According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.
    Type: Grant
    Filed: September 22, 1993
    Date of Patent: April 8, 1997
    Assignees: Fujitsu Ltd., Fujitsu VLSI Ltd.
    Inventors: Rieko Suzuki, Kiyoshi Saida, Kazushige Itazu, Eiji Fujine, Yoshihiro Kamiya, Yoshitaka Uchida, Takako Murakami, Teruhisa Tsuyuki, Kazunori Kawazoe, Takeshi Shimazaki, Yukimi Nishiwaki