Patents by Inventor Takamichi Fukui

Takamichi Fukui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7557408
    Abstract: A semiconductor device has a semiconductor substrate having an impurity-diffused region and a device isolation insulating film formed in the surficial portion thereof, a gate electrode formed on the semiconductor substrate, a contact formed on the gate electrode and connected to the gate electrode, and a protective film disposed between the semiconductor substrate and the gate electrode, below the connecting portion between the gate electrode and the contact, formed wider in width than the gate electrode in a sectional view taken along the direction of gate length of the gate electrode.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: July 7, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Takamichi Fukui
  • Publication number: 20080029900
    Abstract: A semiconductor device has a semiconductor substrate having an impurity-diffused region and a device isolation insulating film formed in the surficial portion thereof, a gate electrode formed on the semiconductor substrate, a contact formed on the gate electrode and connected to the gate electrode, and a protective film disposed between the semiconductor substrate and the gate electrode, below the connecting portion between the gate electrode and the contact, formed wider in width than the gate electrode in a sectional view taken along the direction of gate length of the gate electrode.
    Type: Application
    Filed: August 2, 2007
    Publication date: February 7, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takamichi FUKUI
  • Publication number: 20020132445
    Abstract: In a method for manufacturing a trench isolation type semiconductor device, a trench is formed within a silicon substrate. Then, a first silicon oxide layer is formed only on a wall of the trench of the silicon substrate by thermally oxidizing the silicon substrate. Then, a second silicon oxide layer is deposited on the first silicon oxide layer by a chemical vapor deposition (CVD) process. Then, a third silicon oxide layer is deposited on the second silicon oxide layer by a plasma CVD process so that the third silicon oxide layer is completely filled in the trench. Then, the third silicon oxide layer outside of the trench is removed so that the third silicon oxide layer is buried in the trench. At least one of the first and second silicon oxide layers is thicker than approximately 60 nm.
    Type: Application
    Filed: February 12, 1999
    Publication date: September 19, 2002
    Inventor: TAKAMICHI FUKUI
  • Patent number: 5994764
    Abstract: A semiconductor device includes a semiconductor substrate, a source and drain, a gate electrode, a first insulating underlayer, and a nitride film. The source and drain are formed on a major surface of the semiconductor substrate to be separated from each other. The gate electrode is formed on the semiconductor substrate between the source and the drain via a gate insulating film. The first insulating underlayer is formed to cover an entire surface of the semiconductor substrate including the gate electrode. The nitride film has a predetermined thickness and is formed on the first insulating underlayer so as to set a distance between the nitride film and the gate insulating film to be 20 times or less the thickness of the nitride film.
    Type: Grant
    Filed: March 18, 1998
    Date of Patent: November 30, 1999
    Assignee: NEC Corporation
    Inventor: Takamichi Fukui