Abstract: An automatic gain control circuit controls a gain of a wireless receiver in accordance with an amplitude of a reception signal. The automatic gain control circuit includes a reference level calculator, a register, a reference level adjuster, and a bit width conversion circuit. The reference level calculator calculates a reference level on the basis of the amplitude of the reception signal. The register stores an adjustment value. The reference level adjuster adjusts the reference level on the basis of the adjustment value stored in the register. The bit width conversion circuit performs a bit width conversion for the entire amplitude direction by changing a bit pitch for determining discrete data values of the reception signal, on the basis of the adjusted reference level.

Abstract: A signal detection circuit includes: a correlation circuit including the first through nth correlators connected sequentially as the first through nth stage correlators and each computing a correlation value between a received signal and a spreading sequence while shifting the received signal to the next stage depending on the chip rate period of the spreading sequence; a first adder that adds k correlation values computed by k correlators so as to generate a first addition value; a second adder that adds r correlation values computed by r correlators so as to generate a second addition value; a subtractor that subtracts the first addition value from the second addition value so as to generate a subtraction value; and a synchronization detection unit that compares the subtraction value with a threshold value, so as to detect the synchronization timing of the spreading sequence and the received signal.

Abstract: An automatic gain control circuit includes a reference level calculator that calculates a reference level on the basis of the amplitude of a reception signal; a resistor that stores an adjustment value for the reference level; a reference level adjuster that adjusts the reference level on the basis of the adjustment value stored in the resistor, and generates an adjusted reference level; and a bit width conversion circuit that performs a bit width conversion to reduce the bit width of the reception signal, on the basis of the adjusted reference level.

Abstract: A signal detection circuit includes: a correlation circuit including the first through nth correlators connected sequentially as the first through nth stage correlators and each computing a correlation value between a received signal and a spreading sequence while shifting the received signal to the next stage depending on the chip rate period of the spreading sequence; a first adder that adds k correlation values computed by k correlators so as to generate a first addition value; a second adder that adds r correlation values computed by r correlators so as to generate a second addition value; a subtractor that subtracts the first addition value from the second addition value so as to generate a subtraction value; and a synchronization detection unit that compares the subtraction value with a threshold value, so as to detect the synchronization timing of the spreading sequence and the received signal.

Abstract: An LPF eliminates noise components from baseband signal obtained by performing a frequency conversion on the received signal on the basis of the received wireless transmission wave. A passband setting part sets the upper limit of frequency of passband in the LPF at a high frequency while a synchronization signal is not detected and at a low frequency after a synchronization signal is detected.

Abstract: A method of generating a clock includes the steps of calculating a first frequency division number through dividing a frequency of an input clock by a target frequency and a specific integer k (k?2); calculating a second frequency division number according to the first frequency division number; dividing a period of time of one cycle of the target frequency by the specific integer k to obtain sections in a number of the specific integer k; dividing the frequency of the input clock with the second frequency division number within one of the sections; dividing the frequency of the input clock with the second frequency division number within each remaining one of the sections in a number of (k?1); and generating the clock having a frequency with one cycle equal to a period of time corresponding to each of the sections.

Abstract: A method of generating a clock includes the steps of calculating a first frequency division number through dividing a frequency of an input clock by a target frequency and a specific integer k (k?2); calculating a second frequency division number according to the first frequency division number; dividing a period of time of one cycle of the target frequency by the specific integer k to obtain sections in a number of the specific integer k; dividing the frequency of the input clock with the second frequency division number within one of the sections; dividing the frequency of the input clock with the second frequency division number within each remaining one of the sections in a number of (k?1); and generating the clock having a frequency with one cycle equal to a period of time corresponding to each of the sections.

Abstract: An FSK demodulator and a method for detecting an inflection point extract a greater amount of effective inflection points of a frequency detection signal while reducing erroneous detection of the inflection points. The inflection point detector includes an inflection point extraction part to extract the inflection point corresponding to variation of a sample value of an amplitude value of the frequency detection signal, an amplitude determination part to determine if a size between peak values of sample values in front and rear of the inflection point exists in a first predetermined range, a preamble determination part to determine if a difference between initial and final sample values of at least one of a symbol having the extracted inflection point and a right before symbol exists in a second predetermined range, and an AND operation part to determine a normal inflection point.

Abstract: An FSK demodulator and a method for detecting an inflection point extract a greater amount of effective inflection points of a frequency detection signal while reducing erroneous detection of the inflection points. The inflection point detector includes an inflection point extraction part to extract the inflection point corresponding to variation of a sample value of an amplitude value of the frequency detection signal, an amplitude determination part to determine if a size between peak values of sample values in front and rear of the inflection point exists in a first predetermined range, a preamble determination part to determine if a difference between initial and final sample values of at least one of a symbol having the extracted inflection point and a right before symbol exists in a second predetermined range, and an AND operation part to determine a normal inflection point.

Abstract: A PHS mobile phone set is provided with an offset estimation device which estimates an offset of a signal received through digital communication and makes use of the estimated offset as correction information for offset correction. The received signal is corrected in offset by use of the estimated offset and then demodulated. In the offset estimation device, the estimated offset is updated on the basis of the control signal indicating whether or not the demodulated digital signal is reliable.

Abstract: A fast Fourier transform circuit includes a computation component, an extraction component and a setting component. The extraction component, at each step of the computation, extracts, from computation result data points calculated by the computation component, data in a pre-specified range with a number of bits the same as a predetermined number of bits, which is an effective range for a butterfly computations. The setting component sets the data points of the predetermined number of bits which have been extracted by the extraction component to serve as input data when butterfly computations of a next step are to be performed by the computation component.

Abstract: A spread spectrum receiver has less symbol detection error due to noise. Correlation values between an input signal and spread code sequences are produced by correlators correspondingly provided for the spread code sequences. When an optimum window width symbol detection window is open, the correlation values are compared with a correlation threshold. When the correlation values exceed the correlation threshold, symbol data of the spread code sequence corresponding to the correlator outputting the correlation value indicating the maximum correlation peak is used to demodulate received symbol data. The optimum window width of the symbol detection window is generated from the correlation values and position information of the correlation peak values. The correlation threshold is updated to the produced correlation threshold. The position information of the correlation peak values is used to adjust the symbol detection window width, thus providing the least symbol detection error.

Abstract: In a synchronous acquisition method of a spread spectrum code, a digital code sequence is generated based on a received radio communication signal. The digital code sequence defines a spread spectrum code which includes a preamble symbol. A plurality of correlation signals are generated based on the spread spectrum code of the digital code sequence. A detection signal is generated in accordance with the correlation signal which corresponds to the preamble symbol. A timing control signal is generated in accordance with the detection signal. A demodulation signal is generated based on the correlation signals and in accordance with the timing control signal. A correction signal is generated based on the demodulation signal. A corrected timing control signal is generated based on the timing control signal and the correction signal, such that the demodulation signal corresponds to the preamble symbol.

Abstract: A PHS mobile phone set is provided with an offset estimation device which estimates an offset of a signal received through digital communication and makes use of the estimated offset as correction information for offset correction. The received signal is corrected in offset by use of the estimated offset and then demodulated. In the offset estimation device, the estimated offset is updated on the basis of the control signal indicating whether or not the demodulated digital signal is reliable.

Abstract: A fast Fourier transform circuit includes a computation component, an extraction component and a setting component. The extraction component, at each step of the computation, extracts, from computation result data points calculated by the computation component, data in a pre-specified range with a number of bits the same as a predetermined number of bits, which is an effective range for a butterfly computations. The setting component sets the data points of the predetermined number of bits which have been extracted by the extraction component to serve as input data when butterfly computations of a next step are to be performed by the computation component.

Abstract: A spread spectrum receiver has less symbol detection error due to noise. Correlation values between an input signal and spread code sequences are produced by correlators correspondingly provided for the spread code sequences. When an optimum window width symbol detection window is open, the correlation values are compared with a correlation threshold. When the correlation values exceed the correlation threshold, symbol data of the spread code sequence corresponding to the correlator outputting the correlation value indicating the maximum correlation peak is used to demodulate received symbol data. The optimum window width of the symbol detection window is generated from the correlation values and position information of the correlation peak values. The correlation threshold is updated to the produced correlation threshold. The position information of the correlation peak values is used to adjust the symbol detection window width, thus providing the least symbol detection error.

Abstract: In a synchronous acquisition method of a spread spectrum code, a digital code sequence is generated based on a received radio communication signal. The digital code sequence defines a spread spectrum code which includes a preamble symbol. A plurality of correlation signals are generated based on the spread spectrum code of the digital code sequence. A detection signal is generated in accordance with the correlation signal which corresponds to the preamble symbol. A timing control signal is generated in accordance with the detection signal. A demodulation signal is generated based on the correlation signals and in accordance with the timing control signal. A correction signal is generated based on the demodulation signal. A corrected timing control signal is generated based on the timing control signal and the correction signal, such that the demodulation signal corresponds to the preamble symbol.