Patents by Inventor Takanori Jin

Takanori Jin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130031323
    Abstract: A memory device sharing system includes M (M represents an integer of 2 or greater) access control apparatus for sharing N (N represents an integer of 2 or greater) memory devices which store data, and a managing apparatus for managing access to the memory devices via the access control apparatus. The managing apparatus checks data stored in the N memory devices, generates data position information representative of the storage positions of data stored in any one of the N memory devices, and sends the data position information to the M access control apparatus. Each of the M access control apparatuses receives the data position information sent from the manager, and accesses the storage position indicated by the data position information if each of the M access control apparatuses receives an access request to access the data from an access request source.
    Type: Application
    Filed: July 19, 2012
    Publication date: January 31, 2013
    Applicants: NEC SOFTWARE TOHOKU, LTD., NEC BIGLOBE, LTD.
    Inventors: Takanori JIN, Ryuichi ISHIGE, Yuji OTSU, Jun OHATA, Koh NAKAHASHI, Kie KAWANA
  • Patent number: 6333212
    Abstract: A semiconductor device with a thickness of 1 mm or less is disclosed, that comprises a frame plate main body with a thickness in the range from 0.1 mm to 0.25 mm, a semiconductor pellet disposed on a first surface of the frame plate main body and with a thickness in the range from 0.2 mm to 0.3 mm, an external connection lead, one end thereof being connected to a peripheral portion of the first surface of the frame plate main body, the other end thereof extending to the outside of the frame plate main body, a bonding wire for electrically connecting an electrode of the semiconductor pellet and a connection portion of the end of the external connection lead, and a sealing resin layer for covering and sealing at least a region including the semiconductor pellet, the bonding wire, and a connection portion.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: December 25, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun Ohmori, Hiroshi Iwasaki, Takuya Takahashi, Takanori Jin, Masatoshi Fukuda
  • Patent number: 6166431
    Abstract: A semiconductor device with a thickness of 1 mm or less is disclosed, that comprises a frame plate main body with a thickness in the range from 0.1 mm to 0.25 mm, a semiconductor pellet disposed on a first surface of the frame plate main body and with a thickness in the range from 0.2 mm to 0.3 mm, an external connection lead, one end thereof being connected to a peripheral portion of the first surface of the frame plate main body, the other end thereof extending to the outside of the frame plate main body, a bonding wire for electrically connecting an electrode of the semiconductor pellet and a connection portion of the end of the external connection lead, and a sealing resin layer for covering and sealing at least a region including the semiconductor pellet, the bonding wire, and a connection portion.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: December 26, 2000
    Assignee: Kabushiki Kaisha Tishiba
    Inventors: Jun Ohmori, Hiroshi Iwasaki, Takuya Takahashi, Takanori Jin, Masatoshi Fukuda
  • Patent number: 6022763
    Abstract: A one-sided sealed type semiconductor device comprising a substrate proper for a one-sided resin mold provided on the first main surface thereof with a wiring circuit including connection parts for semiconductor elements and on the second main surface thereof with flat type external connection terminals led out thereon via a through hole, semiconductor elements set in place and packaged in predetermined areas of the first main surface of the substrate proper, a transfer mold resin layer for sealing solely the surface having the semiconductor elements packaged thereon, and a metallic layer formed on the first main surface independently of wiring circuit and outside the area having the wiring circuit.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: February 8, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun Ohmori, Hiroshi Iwasaki, Takanori Jin
  • Patent number: 5780933
    Abstract: A one-sided sealed type semiconductor device comprising a substrate proper for a one-sided resin mold provided on the first main surface thereof with a wiring circuit including connection parts for semiconductor elements and on the second main surface thereof with flat type external connection terminals led out thereon via a through hole, semiconductor elements set in place and packaged in predetermined areas of the first main surface of the substrate proper, a transfer mold resin layer for sealing solely the surface having the semiconductor elements packaged thereon, and a metallic layer formed on the first main surface independently of wiring circuit and outside the area having the wiring circuit.
    Type: Grant
    Filed: May 10, 1996
    Date of Patent: July 14, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun Ohmori, Hiroshi Iwasaki, Takanori Jin