Patents by Inventor Takanori Okita

Takanori Okita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10037966
    Abstract: The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5a for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5a and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: July 31, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iwasaki, Takeumi Kato, Takanori Okita, Yoshikazu Shimote, Shinji Baba, Kazuyuki Nakagawa, Michitaka Kimura
  • Publication number: 20170092614
    Abstract: The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5a for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5a and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.
    Type: Application
    Filed: December 9, 2016
    Publication date: March 30, 2017
    Inventors: Toshihiro IWASAKI, Takeumi KATO, Takanori OKITA, Yoshikazu SHIMOTE, Shinji BABA, Kazuyuki NAKAGAWA, Michitaka KIMURA
  • Patent number: 8975119
    Abstract: A manufacturing yield of a semiconductor device including a power transistor is improved. When forming a tip portion LE1c of a first lead, a tip portion LE2c of a second lead, and a tip portion LE3c of a third lead by using a spanking die SDM1, the tip portion LE1c of the first lead, the tip portion LE2c of the second lead, and the tip portion LE3c of the third lead are pressed by an upper surface of a protrusion portion provided on a pressing surface of a lower die SD1 and a bottom surface of a groove portion provided in a pressing surface of an upper die SU1, and a bent portion of the second lead and a bent portion of the third lead are pressed by a flat pressing surface of the lower die SD1 and a flat pressing surface of the upper die SU1.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhito Kamachi, Takanori Okita
  • Patent number: 8569163
    Abstract: A risk of an electrical short between electrode pads of a semiconductor device can be reduced to thereby improve quality of the semiconductor device. During ball bonding in wire bonding, in each of the electrode pads of a semiconductor chip which are arrayed along an ultrasonic wave application direction (ultrasonic vibration direction), a ball at the tip of a copper wire and the electrode pad are coupled to each other while being rubbed against each other in a direction intersecting the ultrasonic wave application direction. Thus, the amount of AL splash formed on the electrode pad can be minimized to make the AL splash smaller. As a result, the quality of the semiconductor device assembled by the above-mentioned ball bonding can be improved.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: October 29, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Masahiko Sekihara, Takanori Okita
  • Publication number: 20130244381
    Abstract: A manufacturing yield of a semiconductor device including a power transistor is improved. When forming a tip portion LE1c of a first lead, a tip portion LE2c of a second lead, and a tip portion LE3c of a third lead by using a spanking die SDM1, the tip portion LE1c of the first lead, the tip portion LE2c of the second lead, and the tip portion LE3c of the third lead are pressed by an upper surface of a protrusion portion provided on a pressing surface of a lower die SD1 and a bottom surface of a groove portion provided in a pressing surface of an upper die SU1, and a bent portion of the second lead and a bent portion of the third lead are pressed by a flat pressing surface of the lower die SD1 and a flat pressing surface of the upper die SU1.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 19, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsuhito KAMACHI, Takanori OKITA
  • Publication number: 20120164795
    Abstract: A risk of an electrical short between electrode pads of a semiconductor device can be reduced to thereby improve quality of the semiconductor device. During ball bonding in wire bonding, in each of the electrode pads of a semiconductor chip which are arrayed along an ultrasonic wave application direction (ultrasonic vibration direction), a ball at the tip of a copper wire and the electrode pad are coupled to each other while being rubbed against each other in a direction intersecting the ultrasonic wave application direction. Thus, the amount of AL splash formed on the electrode pad can be minimized to make the AL splash smaller. As a result, the quality of the semiconductor device assembled by the above-mentioned ball bonding can be improved.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 28, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Masahiko Sekihara, Takanori Okita
  • Publication number: 20120098126
    Abstract: The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5a for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5a and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.
    Type: Application
    Filed: October 14, 2011
    Publication date: April 26, 2012
    Inventors: Toshihiro IWASAKI, Takeumi KATO, Takanori OKITA, Yoshikazu SHIMOTE, Shinji BABA, Kazuyuki NAKAGAWA, Michitaka KIMURA
  • Patent number: 7627241
    Abstract: An objective lens system opposing an imaged surface of semiconductor device, and imaging lens system arranged between this objective lens system and image sensor is used to inspect a lower component of the semiconductor device without being influence by an upper component. The F value of objective lens system is made into 1.5 or less, and an imaged surface is photographed and inspected. The imaging lens system also has several lenses with different focal distances. According to the desired magnification, a predetermined lens among the plurality of lenses is arranged in the predetermined location of an optical axis, and the other lenses are evacuated from an optical axis.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: December 1, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Takanori Okita, Kouichi Suzuki
  • Publication number: 20090127315
    Abstract: An apparatus for manufacturing a semiconductor device is provided. The apparatus has a bonding head, a stage, and a system for appropriately setting the amount of a descending movement of the bonding head. The bonding head incorporates a heater. A camera is capable of capturing an image of a gap between the bonding head and the stage under the condition that the bonding head holds a first bonding object and the stage has a second bonding object mounted thereon and before the first and second bonding objects come in contact with each other. A controller calculates the amount of the descending movement of the bonding head based on the image captured by the camera, and causes the bonding head to descend based on the calculated amount of the descending movement.
    Type: Application
    Filed: October 22, 2008
    Publication date: May 21, 2009
    Inventor: Takanori OKITA
  • Publication number: 20060170911
    Abstract: Even when component parts lap up and down spatially on the surface of a semiconductor device, without being influenced by an upper component, an image pick-up and inspection of a lower component is conducted. Having objective lens system opposing the imaged surface of semiconductor device, and imaging lens system arranged between this objective lens system and image sensor, the F value of objective lens system is made into 1.5 or less, and an imaged surface is photoed and inspected. Having objective lens system opposing an imaged surface, and imaging lens system arranged between this objective lens system and imaging surface, and the imaging lens system having several lenses with which focal distances differ, according to the desired magnification, a predetermined lens among the plurality of lenses is arranged in the predetermined location of an optical axis, other lenses are evacuated from an optical axis, and an imaged surface is photoed and inspected.
    Type: Application
    Filed: November 2, 2005
    Publication date: August 3, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Takanori Okita, Kouichi Suzuki
  • Publication number: 20050194423
    Abstract: An ultrasonic bonding device includes a heater plate on which a lead frame having leads is positioned. A semiconductor chip is mounted on the lead frame. A holding member presses the leads of the lead frame against the heater plate. A bonding tool applies ultrasonic energy to a position where a wire is in contact with an electrode of the semiconductor chip so that the wire is bonded to the electrode. The bonding tool also applies ultrasonic energy to a position where the wire is in contact with one of the leads so that the wire is bonded to the lead. A holding surface of the holding member for contact with the leads has a surface roughness higher than that of a supporting surface zone of the heater plate for contact with the leads.
    Type: Application
    Filed: September 10, 2003
    Publication date: September 8, 2005
    Applicant: Renesas Technology Corp.
    Inventor: Takanori Okita
  • Publication number: 20040121513
    Abstract: A die bonding apparatus having a bonding tool which, upon mounting a chip on a substrate, adsorbs and holds the chip, and transports the chip to a die bonding position, and bonds the chip onto a surface of the substrate. The bonding tool includes a bonding head, a motor, a load cell, and a controller. The bonding head adsorbs and holds a chip at its end, and applies bonding load to the chip from above. The motor drives said bonding head to move downward such that said bonding head applies bonding load to the chip. The load cell senses said bonding load applied to the chip. The controller sequentially calculates a command voltage output to said motor taking account of said bonding load fed back from said load cell, and speed-controls said motor load such that the output voltage to said motor gradually decreases in response to increment of said bonding.
    Type: Application
    Filed: June 4, 2003
    Publication date: June 24, 2004
    Applicants: Renesas Technology Corp., Mitsubishi Electric Engineering Company Limited
    Inventors: Katsuhiro Taguchi, Yuichi Tanaka, Toru Kimura, Takanori Okita