Abstract: In a variable resistance circuit included in a internal power supply potential generation circuit of a DRAM, to a fuse for tuning an internal power supply potential, an N channel MOS transistor is connected in parallel. In a pre-LT state return mode, a mode setting signal attains a “H” level to render the N channel MOS transistor conductive, so that the same state as that where no fuse is cut off is established to return the internal power supply potential to a level at a wafer test. It is therefore possible to quickly and accurately review wafer test conditions after a final test.

Abstract: A memory device selling apparatus stores an analytical result of a defective detail in a memory device including fail bits as a result of a test performed in a final test apparatus into a database as memory device information. A customer transmits an acceptable condition of a memory device defective from a customer terminal to the memory device selling apparatus. The memory device selling apparatus searches memory devices fitting the requirement of the customer, creates a combination of the memory devices, and transmits the results thereof to the customer terminal. Thus, the memory device selling apparatus can sell a memory device, even though the device includes a fail bit, without any inconvenience on the customer.

Abstract: In a variable resistance circuit included in a internal power supply potential generation circuit of a DRAM, to a fuse for tuning an internal power supply potential, an N channel MOS transistor is connected in parallel. In a pre-LT state return mode, a mode setting signal attains a “H” level to render the N channel MOS transistor conductive, so that the same state as that where no fuse is cut off is established to return the internal power supply potential to a level at a wafer test. It is therefore possible to quickly and accurately review wafer test conditions after a final test.

Abstract: A one-chip clock synchronized memory device comprises a memory constituted by an ordinary data storage area and a sequence storage area. The sequence storage area sequentially stores logic sequence data including control signals, data signals and address signals. A data area control circuit controls reading and writing of data to and from the ordinary data storage area. Logic sequence data storage means receives logic sequence data and writes the received data to the sequence storage area. The memory device is characterized by its ability to accommodate input data sequentially as logic sequence data while performing ordinary data storage operations.

Abstract: A one-chip flash-memory device includes a flash-memory array, a communications unit for analyzing a serial signal applied to the communications unit and for resolving the serial signal into an address, a command, and data in parallel with each other, and a control unit for controlling rewriting, erasing, and reading operations of the flash-memory array in accordance with the address, the command, and the data of the serial signal received by the communications unit. Rewriting and erasing operations may be performed without dismounting the flash-memory from a circuit board. In addition, the area of the circuit board on which the flash-memory is mounted is advantageously reduced.