Patents by Inventor Takao Akaogi
Takao Akaogi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240029765Abstract: The present disclosure generally relates to circuit architectures for programming and accessing resistive change elements. The circuit architectures can program and access resistive change elements using neutral voltage conditions. The present disclosure also relates to methods for programming and accessing resistive change elements using neutral voltage conditions. The present disclosure additionally relates to sense amplifiers configurable into initializing configurations for initializing the sense amplifiers and comparing configurations for comparing voltages received by the sense amplifiers. The sense amplifiers can be included in the circuit architectures of the present disclosure.Type: ApplicationFiled: October 2, 2023Publication date: January 25, 2024Applicant: Nantero, Inc.Inventors: Takao Akaogi, Jia Luo, Nancy See Loiu Leong
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Patent number: 11817171Abstract: The present disclosure generally relates to circuit architectures for programming and accessing resistive change elements. The circuit architectures can program and access resistive change elements using neutral voltage conditions. The present disclosure also relates to methods for programming and accessing resistive change elements using neutral voltage conditions. The present disclosure additionally relates to sense amplifiers configurable into initializing configurations for initializing the sense amplifiers and comparing configurations for comparing voltages received by the sense amplifiers. The sense amplifiers can be included in the circuit architectures of the present disclosure.Type: GrantFiled: October 8, 2021Date of Patent: November 14, 2023Assignee: Nantero, Inc.Inventors: Takao Akaogi, Jia Luo, Nancy See Loiu Leong
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Publication number: 20220028435Abstract: The present disclosure generally relates to circuit architectures for programming and accessing resistive change elements. The circuit architectures can program and access resistive change elements using neutral voltage conditions. The present disclosure also relates to methods for programming and accessing resistive change elements using neutral voltage conditions. The present disclosure additionally relates to sense amplifiers configurable into initializing configurations for initializing the sense amplifiers and comparing configurations for comparing voltages received by the sense amplifiers. The sense amplifiers can be included in the circuit architectures of the present disclosure.Type: ApplicationFiled: October 8, 2021Publication date: January 27, 2022Applicant: Nantero, Inc.Inventors: Takao Akaogi, Jia Luo, Nancy See Loiu Leong
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Publication number: 20210319812Abstract: The present disclosure generally relates to circuit architectures for programming and accessing resistive change elements. The circuit architectures can program and access resistive change elements using neutral voltage conditions. The present disclosure also relates to methods for programming and accessing resistive change elements using neutral voltage conditions. The present disclosure additionally relates to sense amplifiers configurable into initializing configurations for initializing the sense amplifiers and comparing configurations for comparing voltages received by the sense amplifiers. The sense amplifiers can be included in the circuit architectures of the present disclosure.Type: ApplicationFiled: April 13, 2020Publication date: October 14, 2021Applicant: Nantero, Inc.Inventor: Takao Akaogi
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Patent number: 11145337Abstract: The present disclosure generally relates to circuit architectures for programming and accessing resistive change elements. The circuit architectures can program and access resistive change elements using neutral voltage conditions. The present disclosure also relates to methods for programming and accessing resistive change elements using neutral voltage conditions. The present disclosure additionally relates to sense amplifiers configurable into initializing configurations for initializing the sense amplifiers and comparing configurations for comparing voltages received by the sense amplifiers. The sense amplifiers can be included in the circuit architectures of the present disclosure.Type: GrantFiled: April 13, 2020Date of Patent: October 12, 2021Assignee: Nantero, Inc.Inventor: Takao Akaogi
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Patent number: 11119854Abstract: A method of controlling verification operations for error correction of a non-volatile memory device includes the following. A tolerated error bit (TEB) number for error correction of the non-volatile memory device is set to a first value to control verification operations in accordance with the TEB number. After at least one portion of the non-volatile memory device is programmed for a specific number of times, the TEB number is changed from the first value to a second value to control the verification operations in accordance with the TEB number, wherein the second value is greater than the first value and is less than or equal to the TEB threshold. The method may be performed while the at least one portion of the non-volatile memory device is programmed and verified.Type: GrantFiled: February 14, 2020Date of Patent: September 14, 2021Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventors: Yu-Kuo Yang, Takao Akaogi, Pauling Chen
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Publication number: 20210255921Abstract: A method of controlling verification operations for error correction of a non-volatile memory device includes the following. A tolerated error bit (TEB) number for error correction of the non-volatile memory device is set to a first value to control verification operations in accordance with the TEB number. After at least one portion of the non-volatile memory device is programmed for a specific number of times, the TEB number is changed from the first value to a second value to control the verification operations in accordance with the TEB number, wherein the second value is greater than the first value and is less than or equal to the TEB threshold. The method may be performed while the at least one portion of the non-volatile memory device is programmed and verified.Type: ApplicationFiled: February 14, 2020Publication date: August 19, 2021Inventors: YU-KUO YANG, TAKAO AKAOGI, PAULING CHEN
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Patent number: 10297607Abstract: A non-volatile memory having discrete isolation structures and SONOS (Silicon Oxide Nitride Oxide Silicon) memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.Type: GrantFiled: September 14, 2012Date of Patent: May 21, 2019Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventors: Takao Akaogi, Yider Wu, Yi-Hsiu Chen
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Patent number: 9514824Abstract: A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line.Type: GrantFiled: December 18, 2013Date of Patent: December 6, 2016Assignee: Cypress Semiconductor CorporationInventors: Ya-Fen Lin, Colin S. Bill, Takao Akaogi, Youseok Suh
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Patent number: 8923083Abstract: A method of identifying a damaged bitline address in a non-volatile memory device is introduced. The non-volatile memory device includes a memory cell array and a plurality of bit lines crossing the memory cell array. Each bit line has a first end and a second end. The bit lines are divided into a first group and a second group. The method includes applying a source voltage (charging) or ground voltage (discharging) to a specific group of bit lines, testing the bit lines in two testing stages (open-circuit testing and short-circuit testing) by the principle that no damaged bit line can be charged or discharged, and acquiring an address data of a damaged bit line according to a status data stored in a page buffering circuit and related to whether a bit line is damaged, thereby dispensing with a calculation process for estimating the address of the damaged bit line.Type: GrantFiled: August 23, 2012Date of Patent: December 30, 2014Assignee: Eon Silicon Solution Inc.Inventors: Takao Akaogi, Tony Chan
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Publication number: 20140104957Abstract: A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line.Type: ApplicationFiled: December 18, 2013Publication date: April 17, 2014Applicant: SPANSION LLCInventors: Ya-Fen LIN, Colin BILL, Takao AKAOGI, Youseok SUH
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Publication number: 20140078832Abstract: A non-volatile memory having discrete isolation structures and SONOS memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Applicant: EON SILICON SOLUTION, INC.Inventors: TAKAO AKAOGI, YIDER WU, YI-HSIU CHEN, HUNG-HUI LAI
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Publication number: 20140056088Abstract: A method of identifying a damaged bitline address in a non-volatile memory device is introduced. The non-volatile memory device includes a memory cell array and a plurality of bit lines crossing the memory cell array. Each bit line has a first end and a second end. The bit lines are divided into a first group and a second group. The method includes applying a source voltage (charging) or ground voltage (discharging) to a specific group of bit lines, testing the bit lines in two testing stages (open-circuit testing and short-circuit testing) by the principle that no damaged bit line can be charged or discharged, and acquiring an address data of a damaged bit line according to a status data stored in a page buffering circuit and related to whether a bit line is damaged, thereby dispensing with a calculation process for estimating the address of the damaged bit line.Type: ApplicationFiled: August 23, 2012Publication date: February 27, 2014Inventors: TAKAO AKAOGI, TONY CHAN
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Patent number: 8654591Abstract: In a local word line driver of an NOR flash memory and its flash memory array device, the local word line driver is provided for driving a local word line in a sector of a memory array, and the local word line driver has two transistors including a first transistor and a second transistors, and the first and second transistors are NMOS transistors, and thus achieving the effects of reducing the area occupied by circuits on the local word line driver and the die size, and saving the area for the use by memory units.Type: GrantFiled: December 29, 2010Date of Patent: February 18, 2014Assignee: Eon Silicon Solution Inc.Inventor: Takao Akaogi
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Patent number: 8638609Abstract: A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line.Type: GrantFiled: May 19, 2010Date of Patent: January 28, 2014Assignee: Spansion LLCInventors: Ya-Fen Lin, Colin Bill, Takao Akaogi, Youseok Suh
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Publication number: 20120170377Abstract: In a local word line driver of an NOR flash memory and its flash memory array device, the local word line driver is provided for driving a local word line in a sector of a memory array, and the local word line driver has two transistors including a first transistor and a second transistors, and the first and second transistors are NMOS transistors, and thus achieving the effects of reducing the area occupied by circuits on the local word line driver and the die size, and saving the area for the use by memory units.Type: ApplicationFiled: December 29, 2010Publication date: July 5, 2012Inventor: Takao Akaogi
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Publication number: 20120057406Abstract: A flash memory apparatus includes a plurality of memory sectors and a plurality of path transistors, and each memory sector has a local low voltage line, and each path transistor corresponds to one of the memory sectors, and the path transistors are installed in an alignment direction of the memory sectors. One of the path transistors is installed between two adjacent memory sectors, whose gate is connected to a sector select signal line, and whose drain is connected to the local low voltage line of the corresponding memory sector, and whose source is connected to a global low voltage line, and the global low voltage line is installed at an angle substantially equal to 90 degrees across the gate, so as to save the area occupied by peripheral circuits in the path transistors, and lower the manufacturing cost of the flash memory apparatus.Type: ApplicationFiled: September 2, 2010Publication date: March 8, 2012Applicant: EON SILICON SOLUTION INC.Inventor: TAKAO AKAOGI
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Publication number: 20110286276Abstract: A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line.Type: ApplicationFiled: May 19, 2010Publication date: November 24, 2011Inventors: Ya-Fen LIN, Colin BILL, Takao AKAOGI, Youseok SUH
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Patent number: 7986579Abstract: A device, and corresponding method, includes a temperature dependent bias generator to generate a voltage that is applied to a control gate of a sense amplifier. By applying the temperature dependent bias signal to the sense amplifier, a substantially temperature independent discharge time can be achieved at a sense node of a sense amplifier.Type: GrantFiled: February 13, 2008Date of Patent: July 26, 2011Assignee: Spansion LLCInventor: Takao Akaogi
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Patent number: 7848146Abstract: A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a program inhibited memory cell is turned off and a gating memory cell located on a drain side of the program inhibited memory cell is used to pass a pre-charge voltage to the program inhibited memory cell to provide a pre-charge voltage to a channel of the program inhibited memory cell. Moreover, a pre-charge voltage is passed to a buffering memory cell located on the source side of the program inhibited memory cell to provide a pre-charge voltage to a channel of the buffering memory cell and the gating memory cell that is located on the drain side of the program inhibited memory cell is turned off. During programming, a program voltage is applied to the gate of the program inhibited memory cell where a channel voltage of the program inhibited memory cell is raised above a level raised by the pre-charge voltage.Type: GrantFiled: March 19, 2009Date of Patent: December 7, 2010Assignee: Spansion LLCInventors: Youseok Suh, Ya-Fen Lin, Coling Stewart Bill, Takao Akaogi, Yi-Ching Wu