Patents by Inventor Takao Nishikawa
Takao Nishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7042644Abstract: An optical substrate is manufactured such that a bright color display can be achieved. The optical substrate can be embodied in a display device. As for the optical substrate, a light transmitting layer is formed by bonding a first master having a plurality of color protrusions and a second master having a plurality of curved surface parts with a light transmitting layer precursor disposed therebetween so that the resulting light transmitting layer has a plurality of color recesses transferred from the shape of the color protrusions and a plurality of lenses transferred from the shape of the curved surface parts. The master is separated from the light transmitting layer. The color recesses in the light transmitting layer are filled with pigment to form a color pattern layer. The second master is separated from the light transmitting layer.Type: GrantFiled: August 19, 2003Date of Patent: May 9, 2006Assignee: Seiko Epson CorporationInventor: Takao Nishikawa
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Patent number: 6967114Abstract: A manufacturing method is disclosed for a large EL panel in which a plurality of EL display panels are used. Each of said plurality of EL display panels are constructed of an EL display device and a sub-transparent substrate. The EL display device includes a base layer over which a luminescent material is applied, an electrode layer which is laminated on one side of said base layer, and a TFT layer including a circuit section. The circuit section of a TFT layer is disposed behind an adjacent EL display device. Thus, the EL display devices appear to be unified, forming a large EL display panel. In addition, in the case of in which a plurality of EL display devices are arranged in a matrix pattern, pitch between the pixels provided in the pixel section of the TFT array is maintained constant.Type: GrantFiled: July 14, 2003Date of Patent: November 22, 2005Assignee: Seiko Epson CorporationInventors: Tatsuya Shimoda, Takao Nishikawa
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Publication number: 20050208400Abstract: An organic semiconductor device includes a gate insulating film, an organic semiconductor layer, and a voltage control layer disposed in at least part of an area between the gate insulating film and the organic semiconductor layer and giving an ambipolar characteristic to the organic semiconductor layer.Type: ApplicationFiled: March 21, 2005Publication date: September 22, 2005Inventors: Takao Nishikawa, Yoshihiro Iwasa, Shin-ichiro Kobayashi, Taishi Takenobu
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Patent number: 6913937Abstract: The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance of load capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the memory cell array, and a ferroelectric memory device. In the memory cell array, memory cells formed of ferroelectric capacitors are arranged in a matrix. The ferroelectric capacitors include first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and ferroelectric layers disposed linearly along either the first signal electrodes or the second signal electrodes. Alternatively, the ferroelectric layers may be disposed only in intersection areas of the first and second signal electrodes.Type: GrantFiled: July 15, 2003Date of Patent: July 5, 2005Assignee: Seiko Epson CorporationInventors: Eiji Natori, Kazumasa Hasegawa, Koichi Oguchi, Takao Nishikawa, Tatsuya Shimoda
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Patent number: 6909121Abstract: A method of manufacturing a microlens array substrate is provided comprising the steps of: closely providing a substrate precursor (30) between a first master mold (10) having a plurality of curved surfaces (12) and a second master mold (20) having a plurality of projections (22) to form a substrate (32) having a plurality of lenses (34) formed by the curved surfaces (12) and recesses (36) formed by the projections (22); removing the first and second master molds (10, 20) from the substrate (32); and filling the recesses (36) with a shading material (42) after the second master mold (20) is removed.Type: GrantFiled: April 4, 2003Date of Patent: June 21, 2005Assignee: Seiko Epson CorporationInventor: Takao Nishikawa
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Patent number: 6885050Abstract: A method of manufacturing a ferroelectric memory device includes a step of forming a first region (24) having surface characteristics allowing the material for the members of a ferroelectric capacitor section to be preferentially deposited, and a second region (26) having surface characteristics allowing the material for the capacitor section to be less deposited than the first region (24), and a step of providing the material on the base (10) to form a first electrode (32), a ferroelectric film (34), and a second electrode (36) in the first region (24) of the base (10).Type: GrantFiled: May 24, 2002Date of Patent: April 26, 2005Assignee: Seiko Epson CorporationInventors: Tatsuya Shimoda, Takao Nishikawa
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Publication number: 20050076996Abstract: The object is to provide a manufacturing method of various elastic rollers whose rubber hardness is remarkably reduced. A hollow cylindrical rubber tube (1) is prepared. Thereafter, a metal shaft (2) is inserted in the rubber tube and the rubber tube is secured to the shaft. Thereafter, a coating layer (1a) on the outer peripheral surface of the rubber tube is removed. The rubber roller is located in a chamber and is subject to one or more pressuring operations and one or more evacuating operations to transform the continuous cell rubber layer into an open cell rubber layer. After that, a fluororesin tube is provided to cover the rubber tube or silicone oil is impregnated in the rubber tube, in accordance with the purpose of use of the rubber roller.Type: ApplicationFiled: October 7, 2004Publication date: April 14, 2005Applicant: Mitsumagiken Co., Ltd.Inventor: Takao Nishikawa
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Patent number: 6869171Abstract: This ink jet recording head manufacturing method comprises (A) a process for forming a peeling layer 11 wherein peeling is induced by light irradiation, on a base plate 10 exhibiting light-transmissivity, (B) a process for forming a common electrode film 3 on the peeling layer 11, (C) a process for forming a plurality of piezoelectric elements 4, (D) a process for forming a reservoir piece 5 comprising a lid structure that accommodates in its interior one or more piezoelectric elements 4, which interior forms an ink reservoir 51, (E) a process for irradiating the peeling layer 11 with prescribed light from the base plate 10 side thereof, thereby producing peeling in the peeling layer 11, and peeling the base plate 10 away, and (F) a process for bonding a pressure chamber plate 2, whereon are provided a plurality of pressure chambers 21, to the common electrode film 3 separated from the base plate, so that the pressure chambers 21 are sealed.Type: GrantFiled: December 9, 2002Date of Patent: March 22, 2005Assignee: Seiko Epson CorporationInventors: Takao Nishikawa, Atsushi Takakuwa
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Patent number: 6862783Abstract: An ink jet recording head manufacturing method is provided comprising: forming a peeling layer wherein peeling is induced by light irradiation on a base plate exhibiting light-transmissivity; forming a common electrode film on the peeling layer; forming a plurality of piezoelectric elements, forming a reservoir piece including a lid structure that accommodates one or more piezoelectric elements in an interior which forms an ink reservoir; irradiating the peeling layer with prescribed light from the base plate side to induce peeling; peeling the base plate away; and bonding a pressure chamber plate provided with a plurality of pressure chambers to the common electrode film separated from the base plate so that the pressure chambers are sealed.Type: GrantFiled: December 9, 2002Date of Patent: March 8, 2005Assignee: Seiko Epson CorporationInventors: Takao Nishikawa, Atsushi Takakuwa
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Publication number: 20050032268Abstract: An organic thin film transistor and a method of manufacturing the same are provided. The transistor has a threshold voltage that can be easily controlled without changing the material forming an organic semiconductor film. The organic thin film transistor includes a gate electrode, a gate insulating film, a source electrode, a drain electrode, and an organic semiconductor film. A threshold voltage controlling film is provided between the gate insulating film and the organic semiconductor film.Type: ApplicationFiled: June 30, 2004Publication date: February 10, 2005Inventors: Takao Nishikawa, Tatsuya Shimoda, Yoshihiro Iwasa, Taishi Takenobu, Shinichiro Kobayashi, Tadaoki Mitani
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Patent number: 6842289Abstract: A manufacturing method of a microlens array includes the step of forming second light transmitting layers 36 on a first light transmitting layer 26. The first light transmitting layer 26 has a plurality of recessed parts 28 and partitions 32 for delimiting the recessed parts 28, wherein at least a portion of the inner surface of each recessed part 28 is a lens surface 30. The second light transmitting layers 36 are formed in the respective recessed parts 28 in such a manner that the second light transmitting layers 36 avoid the partitions 32 of the first light transmitting layer 26. The second light transmitting layers 36 are formed in such a manner that the surfaces of the second light transmitting layers 36 form lens surfaces 38 for the respective recessed parts 28.Type: GrantFiled: March 22, 2002Date of Patent: January 11, 2005Assignee: Seiko Epson CorporationInventors: Takao Nishikawa, Atsushi Takakuwa, Mutsumi Tamura
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Publication number: 20040161887Abstract: A ferroelectric memory device of the present invention includes a memory cell array in which memory cells are arranged in a matrix having first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes, and a peripheral circuit section for selectively writing information into or reading information from the memory cell. The memory cell array and the peripheral circuit section are formed in different layers. The peripheral circuit section is formed in a region outside the memory cell array.Type: ApplicationFiled: February 19, 2004Publication date: August 19, 2004Applicant: Seiko Epson CorporationInventors: Kazumasa Hasegawa, Eiji Natori, Takao Nishikawa, Koichi Oguchi, Tatsuya Shimoda
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Patent number: 6757455Abstract: A micromachine and a manufacturing method are provided for a micromachine that has a dynamic first microstructured portion serving as a drive portion, and a static second microstructured portion adapted to perform a switching function and which functions as an optical element. The second microstructured portion can be manufactured at least without complex steps, such as a silicon process, by forming a static second microstructure on the dynamic first microstructured portion, or in such a way as to be overlaid thereon by mold transfer. Thus, the microstructured portion of a complex shape can be easily formed with good reproducibility. When a plurality of elements are arranged in an array, similarly as in the case of a spatial light modulator, the stable reproduction thereof is achieved by the mold transfer. Thus, as compared with the case of manufacturing all elements in a silicon process, the probability of an occurrence of a defect is very low.Type: GrantFiled: June 12, 2000Date of Patent: June 29, 2004Assignee: Seiko Epson CorporationInventors: Shunji Kamijima, Masatoshi Yonekubo, Takashi Takeda, Takao Nishikawa
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Patent number: 6730459Abstract: A method for fabricating a microlens array having a flat surface by a simple process, a microlens array fabricated, thereby and an optical device. The method for fabricating the microlens array includes a first step of bringing a lens side of a microlens array substrate 10 having a plurality of lenses 12 formed thereon into close contact with a flat surface 22 of a master plate 20, in which one surface is the flat surface 22, with a light transmitting layer precursor 30 therebetween; a second step of curing the light transmitting layer precursor 30 to form a light transmitting layer 32; and a third step of releasing the master plate 20 from the light transmitting layer 32.Type: GrantFiled: July 27, 2001Date of Patent: May 4, 2004Assignee: Seiko Epson CorporationInventors: Takao Nishikawa, Atsushi Takakuwa
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Patent number: 6727536Abstract: A ferroelectric memory device of the present invention includes a memory cell array in which memory cells are arranged in a matrix having first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes, and a peripheral circuit section for selectively writing information into or reading information from the memory cell. The memory cell array and the peripheral circuit section are formed in different layers. The peripheral circuit section is formed in a region outside the memory cell array.Type: GrantFiled: August 23, 2001Date of Patent: April 27, 2004Assignee: Seiko Epson CorporationInventors: Kazumasa Hasegawa, Eiji Natori, Takao Nishikawa, Koichi Oguchi, Tatsuya Shimoda
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Patent number: 6705709Abstract: An object of the present invention is to provide a method for manufacturing ink jet recording heads by simple and inexpensive means. In order to realize this object, the present invention forms thin film piezoelectric elements using the so-called transfer method, and joining these to a pressure chamber plate. First, a forming plate 8 is prepared beforehand, provided with concavities 82 corresponding to the shapes of thin film piezoelectric elements 5, and upper electrodes 4 and a piezoelectric film 3 are formed as films inside the concavities 82. Then either a lower electrode or a vibration plate 2 is formed so as to cover the piezoelectric film 3, and the thin film piezoelectric elements 5 are fabricated. A substrate 1 constituting a pressure chamber plate is joined to the thin film piezoelectric elements 5, and the thin film piezoelectric elements 5 are removed from the forming plate 8.Type: GrantFiled: June 25, 2002Date of Patent: March 16, 2004Assignee: Seiko Epson CorporationInventor: Takao Nishikawa
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Publication number: 20040036823Abstract: An optical substrate is manufactured such that a bright color display can be achieved. The optical substrate can be embodied in a display device. As for the optical substrate, a light transmitting layer is formed by bonding a first master having a plurality of color protrusions and a second master having a plurality of curved surface parts with a light transmitting layer precursor disposed therebetween so that the resulting light transmitting layer has a plurality of color recesses transferred from the shape of the color protrusions and a plurality of lenses transferred from the shape of the curved surface parts. The master is separated from the light transmitting layer. The color recesses in the light transmitting layer are filled with pigment to form a color pattern layer. The second master is separated from the light transmitting layer.Type: ApplicationFiled: August 19, 2003Publication date: February 26, 2004Inventor: Takao Nishikawa
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Publication number: 20040014247Abstract: The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the memory cell array, and a ferroelectric memory device. In the memory cell array, memory cells formed of ferroelectric capacitors are arranged in a matrix. The ferroelectric capacitors include first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and ferroelectric layers disposed linearly along either the first signal electrodes or the second signal electrodes. Alternatively, the ferroelectric layers may be disposed only in intersection areas of the first and second signal electrodes.Type: ApplicationFiled: July 15, 2003Publication date: January 22, 2004Applicant: Seiko Epson CorporationInventors: Eiji Natori, Kazumasa Hasegawa, Koichi Oguchi, Takao Nishikawa, Tatsuya Shimoda
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Publication number: 20040014252Abstract: A manufacturing method is disclosed for a large EL panel in which a plurality of EL display panels are used. Each of said plurality of EL display panels are constructed of an EL display device and a sub-transparent substrate. The EL display device includes a base layer over which a luminescent material is applied, an electrode layer which is laminated on one side of said base layer, and a TFT layer including a circuit section. The circuit section of a TFT layer is disposed behind an adjacent EL display device. Thus, the EL display devices appear to be unified, forming a large EL display panel. In addition, in the case of in which a plurality of EL display devices are arranged in a matrix pattern, pitch between the pixels provided in the pixel section of the TFT array is maintained constant.Type: ApplicationFiled: July 14, 2003Publication date: January 22, 2004Applicant: Seiko Epson CorporationInventors: Tatsuya Shimoda, Takao Nishikawa
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Patent number: 6646662Abstract: A template 1 is brought close to or in contact with a surface to be patterned 111 and patterns are formed with liquid 62 on the surface 111. This method comprises the steps of: bringing the template 1 close to or essentially in contact with the surface 111, supplying liquid 62 to a plurality of through holes 12 established in the pattern transfer region 10 of the template 1 for supplying the liquid 62, and separating the template 1 from the surface 111 after the liquid 62 is adhered to the surface 111 via the through holes 12.Type: GrantFiled: May 25, 1999Date of Patent: November 11, 2003Assignee: Seiko Epson CorporationInventors: Satoshi Nebashi, Takao Nishikawa, Tatsuya Shimoda