Abstract: An information recording/reading apparatus employs a preamble to reproduce a clock used when recording information in a recording medium and reads the information out of the recording medium at a timing synchronized with a read signal. The preamble is split and recorded by replacing a middle portion of the preamble with data and a sync byte. While a first buffer is employed to delay signal data read out of the recording medium, a frequency offset detector detects a frequency offset using the split preamble.

Abstract: In a Maximum A posteriori Probability decoding (MAP decoding), a correlation and a deviation of noises for past and future states which depend on input signal patterns in past N bits and future Q bits are calculated by training by a noise correlation arithmetic operating unit 84 and they are stored. Upon reproduction, in a white noise arithmetic operating unit 91, white noise values for the past and future states in which colored noises are converted into white noises are obtained by using the stored correlation and deviation of the noises. In an input signal arithmetic operating unit 92, an input signal (channel information) ?c(yk|Smk) of the MAP decoding is calculated from the white noise values and the deviation for the past and future states. A likelihood in the MAP decoding is obtained from the input signal.

Abstract: A recording and reproducing apparatus includes an RLL encoder that encodes an information bit string to a code bit string and a RLL decoder that decodes the code bit string to the information bit string. The RLL encoder encodes the information bit string to the code bit string of a run-length-limited code at a high encoding rate satisfying a plurality of conditions of constraint regarding a string of successive zeros. The RLL decoder decodes the code bit string encoded by the RLL encoder to the information bit string.

Abstract: In a training operation for optimizing a multiplication coefficient for each tap of an FIR equalizer equalizing a read signal read from a recording medium, as a restricted coefficient updating vector applied for updating the multiplication coefficient for each tap of the FIR filter, a vector is utilized which is obtained by projecting, onto a plane perpendicular to a predetermined restricting conditional vector, a coefficient updating vector determined based on an equalizer error between the output of the FIR equalizer and a reproduction output determined therefrom and a delayed input value for each tap of the FIR equalizer.

Abstract: A record reproduction apparatus includes an encoding unit that encodes sector data to be written into a recording medium, by dividing the data into a predetermined number of blocks, and an iterative decoding unit that iteratively decodes the sector data read from the recording medium, by dividing the sector data into the predetermined number of blocks.

Abstract: An ECC determining unit determines whether an error detected by using an ECC has been corrected. When the detected error has not been corrected, an equalizer output sequence transfer unit transfers an equalizer output sequence yk stored in an equalizer output sequence storage unit to a transfer data storage unit in a hard disk controller, so that a high-performance decoding unit (software) performs repetitive decoding, using the transferred equalizer output sequence yk.

Abstract: An information recording/reading apparatus employs a preamble to reproduce a clock used when recording information in a recording medium and reads the information out of the recording medium at a timing synchronized with a read signal. The preamble is split and recorded by replacing a middle portion of the preamble with data and a sync byte. While a first buffer is employed to delay signal data read out of the recording medium, a frequency offset detector detects a frequency offset using the split preamble.

Abstract: A magnetic head testing apparatus includes reference information storing means for holding a predetermined reference sampling period and a number of reference samplings, sampling means for sampling reproduced data read a plurality of times from a magnetic medium in the reference sampling period, sampling number acquiring means for acquiring a sampling number of measured data from a reproduced data base on a sampling result, sampling number radio calculating means for calculating a ratio of the sampling number of the measured data and the number of reference samplings, sampling data re-acquiring means for changing the sampling period of the measured data depending on the calculated ratio and re-acquiring the sampling data and a measured data overlap-displaying means for overlap-display of the sampling data re-acquired from the measured data a plurality of times.

Abstract: A timing recovery method samples, equalizes and detects a signal reproduced from a recording medium and to output a detection signal, controls sampling positions based on a phase error between the equalized signal and the detection signal, and obtains likelihood information which is related to a bit having a probability of error which exceeds a predetermined value, based on the equalized signal. The control of the sampling positions is suppressed during a time which is based on the likelihood information.

Abstract: A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. Therefore, the timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. After that, while the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.

Abstract: A recording and reproducing apparatus having an error correction function ECC-less, includes a erasure detector generating an erasure flag indicating disappearance of a read signal; and an iterative decoder having two soft-in/soft-out (SISO) decoders, i.e., an inner decoder and an outer decoder, and correcting the erasure by inputting the erasure flag ek into the inner decoder 84 and performing erasure compensation in the inner decoder. As the erasure compensation in the inner decoder, channel information is masked while the erasure flag is on. The erasure of data due to a media defect is detected inside the iterative decoder, and the second erasure flag is inputted into the inner decoder to perform erasure compensation in the inner decoder.

Abstract: A data storage apparatus for magnetic recording and regeneration on a medium. Only in case of a dibit or Tri-bit code sequence in MTR codes having a restricted number of magnetic transition consecutive, a write unit records the interval of the magnetic transition on the medium with an extension of &Dgr;T relative to the original magnetic transition interval. For the maximum likelihood detection after equalization of the medium read signals, a read unit adds to an expected value of the maximum likelihood detection an amplitude error &Dgr;V arising from the extension record of the magnetic transition interval relative to the original magnetic transition interval. A parameter regulation unit regulates and sets &Dgr;T and &Dgr;V by use of test patterns.

Abstract: A recording and reproducing apparatus having an error correction function ECC-less, includes a erasure detector generating an erasure flag indicating disappearance of a read signal; and an iterative decoder having two soft-in/soft-out (SISO) decoders, i.e., an inner decoder and an outer decoder, and correcting the erasure by inputting the erasure flag ek into the inner decoder 84 and performing erasure compensation in the inner decoder. As the erasure compensation in the inner decoder, channel information is masked while the erasure flag is on. The erasure of data due to a media defect is detected inside the iterative decoder, and the second erasure flag is inputted into the inner decoder to perform erasure compensation in the inner decoder.

Abstract: Upon data recording, a data recording unit inserts revise bytes as a predetermined specific code train into at least two or more portions including the head and last portions of data and records the data onto a medium. Upon data reproduction, a data reproducing unit separates a head reproduced signal by using clocks and, thereafter, executes a clock extraction and an amplitude correction by using a signal corresponding to the revise bytes as a specific code train. In principle, an RLL code for the clock extraction and gain tracking is eliminated and, in place of the RLL code, the revise bytes comprising the specific code train are inserted into the data and the data is recorded onto the medium.

Abstract: In a Maximum A posteriori Probability decoding (MAP decoding), a correlation and a deviation of noises for past and future states which depend on input signal patterns in past N bits and future Q bits are calculated by training by a noise correlation arithmetic operating unit 84 and they are stored. Upon reproduction, in a white noise arithmetic operating unit 91, white noise values for the past and future states in which colored noises are converted into white noises are obtained by using the stored correlation and deviation of the noises. In an input signal arithmetic operating unit 92, an input signal (channel information) &Lgr;c(yk|Smk) of the MAP decoding is calculated from the white noise values and the deviation for the past and future states. A likelihood in the MAP decoding is obtained from the input signal.

Abstract: A detection circuit in a magnetic recording and playback apparatus which uses partial response and the maximum likelihood method, in which neither the size of the detection circuit nor the power consumption increase when the partial response order n increases. In this detection circuit, in the circuit that detects a signal read out from a head, either a plurality of equalizers for different target equalization waveforms, or a single variable target equalizer is provided. A detector for the waveform output from an equalizer is connected in series with the detector. A plurality of combinations, each formed by an equalizer and a detector, is connected in parallel to the output of a filter, the outputs of the combinations of equalizers and detectors being input to a switching circuit, which is controlled by a switching control means. The switching control means controls the switching circuit so that just one of the combinations of equalizer and detectors is selected as the detector output.

Abstract: Disclosed are an asymmetrical signal detector for detecting an asymmetrical quantity of an asymmetrical signal and a signal regenerating apparatus using this detector. This detector includes a first delaying element for delaying the input signal, a first subtracting element for subtracting an output of the first delaying element from the input signal, a second delaying element for delaying an output of the first subtracting element, an adding element for adding an output of the second delaying element to an output of the first subtracting element, a gate signal generating element for generating a gate signal by comparing an output of the adding element with a predetermined threshold value, a second subtracting element for subtracting the output of the subtracting element from the input signal and a selecting element for selecting an output of the second subtracting element in accordance with the gate signal, thereby obtaining an offset quantity.

Abstract: A compact card type disk drive includes a housing (21) for accommodating a disk for storing data, a disk drive for rotating the disk, a head assembly for writing and reading data to and from the disk and an electronic circuit including at least an interface circuit (39), the latter three being accommodated in the housing. A connector (42) connected to the electronic circuit is fixed to the outside portion of the housing (21). The electronic circuit preferably contains a read/write circuit (36) and a control circuit (38). The housing (21) preferably includes a lower base (22) and an upper cover (23), and a printed circuit board (14) is disposed along the inner wall of either one, or both, of the base (22) and the cover (23). The outer dimension of the plane of the disk drive is preferably about 85.6 mm.times.54 mm, and typically, the outer thickness is 5 mm. Preferably, one connector (42) is disposed on either one of the minor sides of the housing (21).

Abstract: A compact card type disk a drive includes a housing (21) for accommodating a disk for storing data, a disk drive for rotating the disk, head assembly for writing and reading data to and from the disk and an electronic circuit including at least an interface circuit (39), the latter three being accommodated in the housing. A connector (42) connected to the electronic circuit is fixed to the outside portion of the housing (21). The electronic circuit preferably contains a read/write circuit (36) and a control circuit (38). The housing (21) preferably includes a lower base (22) and an upper cover (23), and a printed circuit board (14) is disposed along the inner wall of either one, or both, of the base (22) and the cover (23). The outer dimension of the plane of the disk drive is preferably about 85.6 mm.times.54 mm, and typically, the outer thickness is 5 mm. Preferably, one connector (42) is disposed on either one of the minor sides of the housing (21).

Abstract: A clock phase acquisition/tracking device comprises a phase error operation section for operating a phase error of a quantized signal to a given quantization timing and a clock generation section for generating a clock at a given phase based on a phase error information operated in the phase error operation section. For the resulting quantized signal, a determination is made using a threshold set based on a previously quantized signal when the phase error is operated in the phase error operation section upon the beginning of the clock phase acquisition. Thus, the time necessary for the phase aquisition can be shortened.