Patents by Inventor Takao Yonehara

Takao Yonehara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8237761
    Abstract: A novel semiconductor article manufacturing method and the like are provided. A method of manufacturing a semiconductor article having a compound semiconductor multilayer film formed on a semiconductor substrate includes: preparing a member including an etching sacrificial layer (1010), a compound semiconductor multilayer film (1020), an insulating film (2010), and a semiconductor substrate (2000) on a compound semiconductor substrate (1000), and having a first groove (2005) which passes through the semiconductor substrate and the insulating film, and a semiconductor substrate groove (1025) which is a second groove provided in the compound semiconductor multilayer film so as to be connected to the first groove, and bringing an etchant into contact with the etching sacrificial layer through the first groove and then the second groove and etching the etching sacrificial layer to separate the compound semiconductor substrate from the member.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: August 7, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Kenji Yamagata, Yoshinobu Sekiguchi, Kojiro Nishi
  • Publication number: 20120171866
    Abstract: According to a method for transferring a functional region, at least part of functional regions on separation layers arranged on a first substrate is transferred onto a second substrate, the separation layers being capable of being brought into a separable state by treatment. In a first bonding step, the first substrate is bonded to the second substrate with a dry film resist arranged between the second substrate and the at least part of the functional regions above the first substrate. In an exposure step, at least part of the dry film resist is exposed. In a patterning step, the exposed dry film resist is patterned.
    Type: Application
    Filed: September 14, 2010
    Publication date: July 5, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Takao Yonehara
  • Publication number: 20120145553
    Abstract: This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Application
    Filed: November 3, 2011
    Publication date: June 14, 2012
    Applicant: SOLEXEL, INC.
    Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Subramanian Tamilmani, George D. Kamian, Jay Ashjaee, Takao Yonehara
  • Publication number: 20120138455
    Abstract: An apparatus for anodizing substrates immersed in an electrolyte solution. A substrate holder mounted in a storage tank includes a first support unit having first support elements for supporting, in a liquid-tight condition, only lower circumferential portions of the substrates, and a second support unit attachable to and detachable from the first support unit and having second support elements for supporting, in a liquid-tight condition, remaining circumferential portions of the substrates. A drive mechanism separates the first support unit and the second support unit when loading and unloading the substrates, and for connecting the first support unit and the second support unit after the substrates are placed in the substrate holder.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 7, 2012
    Inventors: Yasuyoshi MIYAJI, Noriyuki HAYASHI, Takamitsu INAHARA, Takao YONEHARA, Karl-Josef KRAMER, Subramanian TAMILMANI
  • Publication number: 20120085278
    Abstract: High productivity thin film deposition methods and tools are provided wherein a thin film semiconductor material layer with a thickness in the range of less than 1 micron to 100 microns is deposited on a plurality of wafers in a reactor. The wafers are loaded on a batch susceptor and the batch susceptor is positioned in the reactor such that a tapered gas flow space is created between the susceptor and an interior wall of the reactor. Reactant gas is then directed into the tapered gas space and over each wafer thereby improving deposition uniformity across each wafer and from wafer to wafer.
    Type: Application
    Filed: June 9, 2011
    Publication date: April 12, 2012
    Applicant: SOLEXEL INC.
    Inventors: Mehrdad M. Moslehi, Karl-Josef Kramer, Jay Ashjaee, George D. Kamian, David Mordo, Takao Yonehara
  • Publication number: 20120038039
    Abstract: A conventional transfer technique has low efficiency in separation at a separation layer and costs much. The present invention is characterized in that a plurality of second integrated circuits of smaller chip size than that of a first integrated circuit provided on a first substrate are formed in a semiconductor layer formed on a separation layer provided on a second semiconductor substrate, at least the semiconductor layer is separated for each second integrated circuit so that the end surfaces of the separation layer are inclined or curved, the first semiconductor substrate is bonded to the second semiconductor substrate, and a bonded structure is separated along the separation layer.
    Type: Application
    Filed: March 29, 2010
    Publication date: February 16, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Kiyofumi Sakaguchi, Takao Yonehara
  • Publication number: 20120034759
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a plurality of first integrated circuits on the surface side of a first semiconductor substrate; forming a plurality of second integrated circuits in a semiconductor layer that is formed on a release layer provided on a second semiconductor substrate; bonding the two semiconductor substrates so that electrically bonding portions are bonded to each other to form a bonded structure; separating the second semiconductor substrate from the bonded structure at the release layer to transfer, to the first semiconductor substrate, the semiconductor layer in which the plurality of second integrated circuits are formed; and dicing the first semiconductor substrate to obtain stacked chips each including the first integrated circuit and the second integrated circuit.
    Type: Application
    Filed: April 2, 2010
    Publication date: February 9, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Kiyofumi Sakaguchi, Takao Yonehara, Nobuo Kawase, Kenji Nakagawa
  • Publication number: 20120028414
    Abstract: A method of manufacturing a semiconductor chip including an integrated circuit and a through-electrode penetrating a semiconductor layer includes the steps of preparing a first substrate including a release layer and a semiconductor layer formed on the release layer; forming an integrated circuit in the semiconductor layer; forming, in the semiconductor layer, a hole or groove having a depth that does not reach the release layer; filling the hole or the groove with an electrical conductor; bonding a second substrate to the semiconductor layer to form a bonded structure; separating the bonded structure at the release layer to prepare the second substrate to which the semiconductor layer is transferred; and removing at least a portion of the reverse surface side of the semiconductor layer exposed by the separation to expose the bottom of the electrical conductor.
    Type: Application
    Filed: April 2, 2010
    Publication date: February 2, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Takao Yonehara, Kiyofumi Sakaguchi, Nobuo Kawase, Kenji Nakagawa
  • Publication number: 20110311276
    Abstract: Provided is a method for transferring, onto a second substrate, at least one of functional regions arranged and joined to a first separation layer that is disposed on a first substrate and that becomes separable by a treatment, in which regions on the second substrate where the functional regions are to be transferred have a second separation layer that becomes separable by a treatment. The method includes a step of joining the first substrate to the second substrate by bonding such that the functional regions contact the second separation layer; a step of separating the functional regions from the first substrate at the first separation layer; and a step of, before or after the step of separation, forming separation grooves penetrating through the second substrate and the second separation layer from a surface of the second substrate, the surface being opposite to a surface having the second separation layer thereon.
    Type: Application
    Filed: March 1, 2010
    Publication date: December 22, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Takao Yonehara, Yasuyoshi Takai
  • Patent number: 8053335
    Abstract: A method includes forming a first layer containing silicon oxide on a first substrate, partially removing the first layer to form an exposure portion on the first substrate, depositing amorphous gallium nitride system compound semiconductor on the first substrate with the exposure portion, evaporating the semiconductor on the first layer to form cores of the semiconductor on the exposure portion of the first substrate, forming an epitaxial layer of the semiconductor on the first substrate, and removing the epitaxial layer of the semiconductor on the exposure portion on the first substrate to form a separating groove.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: November 8, 2011
    Inventor: Takao Yonehara
  • Publication number: 20110256654
    Abstract: This disclosure presents manufacturing methods and apparatus designs for making TFSSs from both sides of a re-usable semiconductor template, thus effectively increasing the substrate manufacturing throughput and reducing the substrate manufacturing cost. This approach also reduces the amortized starting template cost per manufactured substrate (TFSS) by about a factor of 2 for a given number of template reuse cycles.
    Type: Application
    Filed: February 12, 2011
    Publication date: October 20, 2011
    Applicant: SOLEXEL, INC.
    Inventors: Mehrdad M. Moslehi, Karl-Josef Kramer, David Xuan-Qi Wang, Pawan Kapur, Somnath Nag, George D Kamian, Jay Ashjaee, Takao Yonehara
  • Patent number: 8035668
    Abstract: An exposure apparatus which forms a pattern on an object. The apparatus includes an exposure head structure in which a plurality of elemental exposure units are arrayed, each elemental exposure unit including (i) at least one light source for emitting exposure light and (ii) an optical element which forms an image of the at least one light source on the object, for exposing the object. Positions of the images of the at least one light source in a direction perpendicular to a surface of the object include plural positions different from each other. A sensor detects a position of the surface of the object and produces a detection result. A controller receives the detection result and controls the exposure head structure such that a pattern is formed on the object by the exposure is selected to expose the object based on the detection result by the sensor.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: October 11, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mitsuro Sugita, Kazuaki Ohmi, Takao Yonehara, Toshihiko Tsuji, Takaaki Terashi, Tohru Kohda, Shinji Tsutsui
  • Patent number: 7943488
    Abstract: A method includes placing a first bonding layer on at least one of a first functional region bonded on a release layer with a light releasable adhesive layer on a first substrate, and a transfer region on a second substrate; bonding the first functional region to the second substrate by the first bonding layer; irradiating the release layer with light with a light blocking member being provided to separate the first substrate from the first functional region at the release layer; placing a second bonding layer on at least one of a second functional region on the first substrate, and a transfer region on the release layer or a transfer region on a third substrate; bonding the second functional region to the second substrate or the third substrate by the second bonding layer; and separating the first substrate from the second functional region at the release layer.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: May 17, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takao Yonehara
  • Patent number: 7944564
    Abstract: An information-acquiring device for acquiring information on an objective substance to be detected, which is provided with a sensing element that has a surface capable of fixing the objective substance to be detected thereon, and makes applied light change its wavelength characteristics in response to the fixed state of the objective substance to be detected onto the surface, a light source, and light-receiving means for receiving light emitted from the light source through the sensing element, has the light-receiving means and the light source arranged on the same substrate so that the light which has been emitted from the light source and has been transmitted through the sensing element can be led to the light-receiving means, and has means for varying the wavelength regions of each light incident on each of a plurality of the light-receiving means installed in an optical path from the light source to the light-receiving means.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: May 17, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Norihiko Utsunomiya, Mitsuro Sugita, Satoru Nishiuma, Takao Yonehara
  • Patent number: 7919381
    Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: April 5, 2011
    Assignees: Canon Kabushiki Kaisha, The Board of Trustees of the Leland Stanford Junior University
    Inventors: Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara
  • Publication number: 20110030610
    Abstract: This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation).
    Type: Application
    Filed: May 5, 2010
    Publication date: February 10, 2011
    Applicant: SOLEXEL, INC.
    Inventors: George D. Kamian, Somnath Nag, Subbu Tamilmani, Mehrdad M. Moslehi, Karl-Josef Kramer, Takao Yonehara
  • Publication number: 20110013926
    Abstract: A light-emitting unit having an arrayed light source comprises a substrate; an arrayed light source group containing the arrayed light source arranged in a first direction; a lens array for focusing the light emitted from light emitting elements constituting the arrayed light source; and a lens support having a cavity formed between arrayed light source group and the lens array; the lens support having a first hole for introducing a fluid into the cavity, and a second hole for discharging the introduced fluid in a second direction crossing the first direction.
    Type: Application
    Filed: April 28, 2009
    Publication date: January 20, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Takao Yonehara
  • Patent number: 7829362
    Abstract: A sensor which has high measuring sensitivity and is excellent in response is provided by forming a porous film in a sensitive section of a field-effect transistor. It comprises a porous body, which is formed on a sensitive section (here, a gate insulating film) of the field-effect transistor and has cylindrical pores which are formed almost perpendicularly to a substrate, and the field-effect transistor. It uses as a porous film a porous film which is made of a semiconductor material whose main component (except oxygen) is silicon, germanium, or a composite of silicon and germanium, or a porous film made of an insulation material whose main component is silicon oxide, which has pores perpendicular to the substrate.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: November 9, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuhiko Fukutani, Takao Yonehara, Hirokatsu Miyata, Yohei Ishida, Tohru Den
  • Patent number: 7786495
    Abstract: A light-emitting element array can be manufactured without the separation of a metal reflection layer. The light-emitting element array includes a plurality of light-emitting element portions provided on a substrate, at least one space of the spaces between adjacent light-emitting element portions being electrically separated from each other, wherein the metal reflection layer is provided on the substrate and under the plurality of light-emitting element portions, and a resistive layer for electrical separation between the light-emitting element portions is provided between the plurality of light-emitting element portions and the metal reflection layer. The plurality of light-emitting element portions are divided into a plurality of blocks. Each of the blocks includes a plurality of light-emitting portions. The electrical separation between the light-emitting portions can be made as electrical separation between adjacent light-emitting element portions in adjacent and different blocks.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: August 31, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tetsuya Takeuchi, Makoto Koto, Kenji Yamagata, Yoshinobu Sekiguchi, Takao Yonehara
  • Patent number: 7772078
    Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: August 10, 2010
    Assignees: The Board of Trustees of the Leland Stanford Junior University, Canon Kabushiki Kaisha
    Inventors: Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara