Patents by Inventor Takashi Ajima
Takashi Ajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 4853760Abstract: A semiconductor device has a passivation layer including a polyimide film. Argon ions are implanted in the polyimide film to convert it into an electrically stable insulating film.Type: GrantFiled: August 25, 1987Date of Patent: August 1, 1989Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Masahiro Abe, Masaharu Aoyama, Jiro Ohshima, Takashi Ajima
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Patent number: 4636832Abstract: A semiconductor device with a bonding section comprising a semiconductor substrate, a silicon layer formed on the semiconductor substrate with a first insulating layer interposed therebetween, and a bonding pad formed on the silicon layer with a second insulating layer interposed therebetween. The silicon layer has substantially the same size as the bonding pad. When a lead line is bonded to the bonding pad, the silicon layer lessens the stress caused by the bonding.Type: GrantFiled: March 4, 1986Date of Patent: January 13, 1987Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Masahiro Abe, Masaharu Aoyama, Takashi Ajima, Toshio Yonezawa
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Patent number: 4618878Abstract: A semiconductor device having a multilayer wiring structure which comprises a semiconductor substrate, a first wiring layer deposited on said substrate, and a second wiring layer deposited on said first wiring layer with insulating layers disposed therebetween, wherein the insulating interlayer consists of an inorganic insulating layer and a polyimide-based resin film overlying the inorganic insulating layer. The thickness ratio of the polyimide-based resin film to the inorganic insulating film ranges from 0.1 to 0.5. A method of manufacturing a semiconductor device of a multilayer wiring structure wherein an opening is formed in the insulating interlayer to have a small step.Type: GrantFiled: June 15, 1984Date of Patent: October 21, 1986Assignee: Kabushiki Kaisha ToshibaInventors: Masaharu Aoyama, Masahiro Abe, Takashi Ajima, Toshio Yonezawa
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Patent number: 4613888Abstract: A semiconductor device is disclosed which includes a multilayer formed of a hard inorganic main insulation film and a soft subinsulation film as insulation interlayers, and a hard inorganic insulation film as a final passivation film. The final passivation film is directly deposited on the hard inorganic main insulation film of the multilayer.Type: GrantFiled: July 24, 1984Date of Patent: September 23, 1986Assignee: Kabushiki Kaisha ToshibaInventors: Yasukazu Mase, Masahiro Abe, Masaharu Aoyama, Takashi Ajima
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Patent number: 4560642Abstract: A method of manufacturing a semiconductor device which comprises the step of applying a silicon carbide film having a prescribed perforated pattern as a masking film selectively to etch a silicon dioxide film or diffuse an impurity into a substrate.Type: GrantFiled: July 19, 1984Date of Patent: December 24, 1985Assignee: Toyko Shibaura Electric Co., Ltd.Inventors: Toshio Yonezawa, Takashi Ajima, Shunichi Hiraki, Yutaka Koshino, Yoshitami Oka
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Patent number: 4520041Abstract: A metallization structure having a substantially flat surface can be formed on a semiconductor substrate by forming first and second insulating layers on the substrate. The second insulating layer is selectively removed to form grooves therein. Then, a metallic material layer is conformably formed. The metallic layer has grooves corresponding to the grooves of the second insulating layer. A flowable polymer is applied to the surface of the resultant structure to form a layer having a flat surface. The polymer layer and the metallic layer are sequentially ion-etched to expose the second insulating layer. Thus, the metallization structure constituted by the remaining metallic layer and the second insulating layer is formed to have a flat surface.Type: GrantFiled: November 3, 1983Date of Patent: May 28, 1985Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Masaharu Aoyama, Masahiro Abe, Takashi Ajima, Toshio Yonezawa
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Patent number: 4515642Abstract: In a method of producing a semiconductor device, an alumina layer is formed directly on a principal surface of a silicon substrate; aluminum and silicon are ion-implanted through the alumina layer into said substrate; and the substrate is thereafter annealed. The ion-implanted silicon yields better crystalline structure and increases the solid solubility limit of aluminum.Type: GrantFiled: August 22, 1983Date of Patent: May 7, 1985Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Takashi Ajima, Jiro Ohshima, Yutaka Koshino
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Patent number: 4479830Abstract: A method for manufacturing a semiconductor device is shown which includes a step of ion implanting an impurity into an impurity-region formation region of a semiconductor substrate. Before or after the ion implantation step, silicon ions are implanted in a dose of 1.times.10.sup.13 to 1.times.10.sup.15 /cm.sup.2 into the impurity-region formation region and then the silicon ions so implanted are subjected to an activation treatment to form an epitaxial grown protrusion on the surface of the substrate. The protrusion is used as an alignment mark in the subsequent mask alignment step for photolithography.Type: GrantFiled: January 31, 1983Date of Patent: October 30, 1984Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Yutaka Koshino, Jiro Ohshima, Takashi Ajima, Toshio Yonezawa
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Patent number: 4462856Abstract: A system is adapted to etch an aluminium film on a semiconductor wafer into a predetermined pattern by immersing the film in an etching solution. The system comprises a voltage detecting circuit for detecting a voltage created between a platinum electrode and the aluminium film on the semiconductor wafer which are immersed in the etching solution, a comparator for comparing a reference voltage with the voltage detected by the voltage detecting circuit to produce an output signal, and a timer for starting a time count operation upon receipt of the output signal from the comparator and for producing an etching completion signal when it continuously receives the output signal from the comparator for a predetermined time period.Type: GrantFiled: February 17, 1983Date of Patent: July 31, 1984Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Masahiro Abe, Toshio Yonezawa, Masaharu Aoyama, Takashi Ajima
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Patent number: 4426234Abstract: The invention discloses a method for fabricating a semiconductor device comprising the steps of: forming, on an entire surface of a semiconductor substrate of one conductivity type, a first thin film of a diffusion coefficient greater than a diffusion coefficient of the substrate; forming, on an entire surface of the first thin film, a second thin film having a diffusion coefficient smaller than the diffusion coefficient of the first thin film; ion-implanting an impurity through the second thin film into the first thin film to form an impurity region, said impurity having a conductivity type opposite to the conductivity type of the substrate; and effecting annealing to set a junction depth of the impurity region to a predetermined value. According to the method of the invention, an impurity region having a desired sheet resistivity and a desired diffusion depth can be formed in the semiconductor substrate with excellent reproducibility and control.Type: GrantFiled: December 3, 1981Date of Patent: January 17, 1984Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Jiro Ohshima, Yutaka Koshino, Takashi Ajima, Toshio Yonezawa
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Patent number: 4415372Abstract: The invention provides a method for fabricating a semiconductor device which comprises the steps of ion-implanting an impurity into a monocrystalline semiconductor substrate; irradiating the region into which the impurity ions have been implanted with an accelerated electron beam under the conditions that the acceleration voltage is 20 to 200 KeV, and the current is 0.01 to 1 mA and the exposure dose is 10.sup.20 to 10.sup.15 /cm.sup.2 ; and carrying out annealing to form a semiconductor region of one conductivity type. According to the present invention, a semiconductor device can be fabricated which has fewer lattice defects and in which the lifetime of the carriers is long.Type: GrantFiled: October 20, 1981Date of Patent: November 15, 1983Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Yutaka Koshino, Toshio Yonezawa, Takashi Ajima, Jiro Ohshima
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Patent number: 4404736Abstract: A method for manufacturing a semiconductor device of mesa type comprises forming mesa recesses of predetermined depth around an element in the surface of a semiconductor body, forming on the back of semiconductor body a film for lessening the concentration of stress, filling glass powder into mesa recesses, and sintering glass powder to form glass insulators. According to the method of the present invention, cracks can be prevented from being caused in the semiconductor body and glass insulators formed in mesa recesses.Type: GrantFiled: November 9, 1981Date of Patent: September 20, 1983Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Yutaka Koshino, Takashi Ajima, Jiro Ohshima, Masahiro Abe
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Patent number: 4351894Abstract: A method of manufacturing a semiconductor device which comprises the step of applying a silicon carbide film having a prescribed perforated pattern as a masking film selectively to etch a silicon dioxide film or diffuse an impurity into a substrate.Type: GrantFiled: May 12, 1981Date of Patent: September 28, 1982Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Toshio Yonezawa, Takashi Ajima, Shunichi Hiraki, Yutaka Koshino, Yoshitami Oka
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Patent number: 4224636Abstract: A semiconductor device comprising a semiconductor substrate and protective films formed thereon. The protective films comprise at least one silicon carbide film which may be pure or may contain particular impurities.Type: GrantFiled: June 14, 1978Date of Patent: September 23, 1980Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Toshio Yonezawa, Takashi Ajima, Masato Uchida
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Patent number: 4161743Abstract: A semiconductor device includes a semiconductor substrate and a silicon carbide film formed in direct contact with the surface of the semiconductor substrate. The silicon carbide film may have a proper purity or include at least one element selected from the group consisting of hydrogen, oxygen, nitrogen, helium, argon or chlorine.Type: GrantFiled: June 14, 1978Date of Patent: July 17, 1979Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Toshio Yonezawa, Takashi Ajima, Masato Uchida
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Patent number: 4146413Abstract: A method of producing a semiconductor device, comprising the steps of forming a polycrystalline semiconductor layer on the exposed surface of a single crystalline semiconductor substrate, the substrate containing an impurity of one conductivity type and the polycrystalline layer an impurity of the other conductivity type, and heating the polycrystalline layer for the activation thereof at a temperature substantially preventing the impurity contained therein from being diffused into the substrate. The crystal of the substrate is kept free from lattice defect since the impurity is not diffused thereinto. In addition, this method prevents a short circuit from occurring between semiconductor regions of differing conductivity types which would otherwise be caused by deviation in the location of a mask used in the photoetching step.Type: GrantFiled: November 2, 1976Date of Patent: March 27, 1979Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Toshio Yonezawa, Toshio Mitsuno, Kiyoshi Takaoki, Takashi Ajima
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Patent number: 4123564Abstract: A method of producing a semiconductor device comprises removing all of the masking films used for forming desired semiconductor regions in the substrate, newly forming a first insulation film and selectively forming a second insulation film on predetermined portions of the first insulation film by the use of a polycrystalline silicon film as the mask.Type: GrantFiled: December 2, 1976Date of Patent: October 31, 1978Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Takashi Ajima, Kiyoshi Takaoki, Toshio Yonezawa