Abstract: Provided is a ??T cell for securing the purity and number of cells sufficient for treatment. Also provided is a method of generating the ??T cell. More specifically, provided are homogeneous ??T cells excellent in that the ??T cells are not affected by exhaustion of the cells. The foregoing is achieved by ??T cells obtained by subjecting induced pluripotent stem cells (iPS cells) to differentiation induction treatment. Specifically, the foregoing is achieved by ??T cells generated by subjecting iPS cells having a rearranged ??TCR gene (??TCR-type iPS cells) to differentiation induction treatment. According to the method of generating the ??T cell of the present invention, there can be provided ??T cells and a cell population of ??T cells that have an excellent function of having antigen-specific cytotoxic activity in a MHC-unrestricted manner, and that are more homogeneous and have a higher effect than ??T cells separated from peripheral blood.

Abstract: The present invention provides a method for maintenance and expansion of a colon cancer stem cell or induction of a colon cancer organoid. In addition, the present invention provides a medicament screening system using a colon cancer stem cell maintained and expanded or a colon cancer organoid induced by the method.

Abstract: Provided is a method of generating iPS cells. Specifically, provided is a method of generating iPS cells having a rearranged ??-TCR gene. Also provided is a cell population including the generated iPS cells. The method includes stimulating collected blood cells with IL-2 and a bisphosphonate, and then introducing cell reprogramming factors through use of a Sendai virus (SeV) vector. According to the method of the present invention, iPS cells having a rearranged ??-TCR gene can be effectively generated. In particular, the method may be free of a step of treating the blood cells with an antibody before the step of stimulating blood cells with any one kind or a plurality of kinds of interleukins selected from IL-2, IL-15, and IL-23, and a bisphosphonate. In addition, iPS cells generated by the method of the present invention can be differentiated into desired cells by differentiation induction treatment.

Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

Abstract: A semiconductor integrated device including a capacitor having a structure suitable for a larger capacitance is disclosed. A first electrode layer is electrically isolated by a first device isolation layer. An interelectrode insulating film is formed on the first electrode layer and the first device isolation layer and having an opening extending to the first electrode layer. A first electrode portion is formed on the interelectrode insulating film and electrically connected to the first electrode layer through the opening. A second electrode portion is formed on the interelectrode insulating film and electrically isolated from the first electrode layer. A third electrode portion is formed so as to penetrate through the interelectrode insulating film from a lower surface of the second electrode portion formed above the first device isolation layer, then to protrude inside the first device isolation layer, and to face side surfaces of the first electrode layer.

Abstract: A semiconductor memory device includes a memory cell block. The memory cell block includes a plurality of n-type first MIS transistors with current passages connected in series. Each of the first MIS transistors includes a source, a drain, and a charge storage layer formed on a (001)-plane of a semiconductor substrate with a gate insulating film interposed therebetween and is configured to store data. A direction from the source to the drain in each of the first MIS transistors is set parallel to a [001]-direction or [010]-direction of the semiconductor substrate.

Abstract: This semiconductor device comprises a semiconductor substrate with a first impurity type; a plurality of active areas formed in the semiconductor substrate; an element isolation trench including a first trench part and a second trench part surrounding the plurality of active areas, the first trench part being extended from a surface of the semiconductor substrate to a depth direction, the second trench part being extended from the center of a bottom surface of the first trench part to the depth direction with a narrower width than the width of the first trench part in a width direction; an element isolation insulator film filled in the element isolation trench; a gate electrode formed on the plurality of active areas via a gate insulator film; a plurality of diffusion layers with a second impurity type formed in a surface of the plurality of active areas, the plurality of diffusion layers being located on each side of the element isolation trench and separated each other on each side of the gate electrode; an

Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

Abstract: A semiconductor memory device includes a memory cell block. The memory cell block includes a plurality of n-type first MIS transistors with current passages connected in series. Each of the first MIS transistors includes a source, a drain, and a charge storage layer formed on a (001)-plane of a semiconductor substrate with a gate insulating film interposed therebetween and is configured to store data. A direction from the source to the drain in each of the first MIS transistors is set parallel to a [001]-direction or [010]-direction of the semiconductor substrate.

Abstract: A method of producing acrylic resin for use as a film and having reduced tendency to stress whitening and acrylic resins produced by such method. An elastomer is prepared by copolymerizing a cross-linking monomer with a monomer mixture comprising a major proportion of acrylic acid alkyl ester containing 1 to 8 carbon atoms in the alkyl group and having gel content of more than 60%, degree of swelling of less than 15 and mean particle size of 500 to 2000 A. A resin component comprising a major proportion of methacrylic acid alkyl ester containing 1 to 4 carbon atoms in the alkyl group is graft polymerized to a degree of grafting of over 30% in an emulsion of the elastomer to produce the desired resin.

Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.