Patents by Inventor Takashi Hisada

Takashi Hisada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230178404
    Abstract: Handler wafers and methods of handling a wafer include positioning a handler, which is attached to a wafer by a bonding layer that comprises a debonding layer, an optical enhancement layer, and an anti-reflection layer. The handler is debonded from the wafer using a laser that emits laser energy at a wavelength that is absorbed by the debonding layer and that is confined to the debonding layer by the optical enhancement layer, such that the material of the debonding layer ablates when exposed to the laser energy to release the wafer.
    Type: Application
    Filed: December 3, 2021
    Publication date: June 8, 2023
    Inventors: Akihiro Horibe, Qianwen Chen, RISA MIYAZAWA, Michael P. Belyansky, John Knickerbocker, Takashi Hisada
  • Publication number: 20230154887
    Abstract: An apparatus for injecting solder material in via holes located in a top surface of a wafer is provided. The apparatus includes an injection head having a contact surface for contacting the top surface of the wafer, and at least one aperture for injecting the solder material though the injection head into the via holes. The apparatus further includes an evacuating device connected to the injection head for evacuating gas from the via holes. The injection head has a chamfer part on an edge of a contact surface contacting the top surface of the wafer.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 18, 2023
    Inventors: Sayuri Hada, Toyohiro Aoki, Takashi Hisada, Shintaro Yamamichi
  • Publication number: 20230051337
    Abstract: A method of fabricating a bridged multi-chip assembly structure includes providing a carrier substrate. The method further includes arranging a plurality of chips on the carrier substrate in a predetermined layout. Each chip has a front surface including a set of terminals formed thereon. The method further includes depositing a molding material between the plurality of chips and on the carrier substrate. The method further includes removing the carrier substrate from the plurality of chips fixed by the molding material. The method further includes bonding a bridge chip to corresponding sets of terminals of at least two chips of the plurality of chips fixed by the molding material.
    Type: Application
    Filed: August 16, 2021
    Publication date: February 16, 2023
    Inventors: Akihiro Horibe, Toyohiro Aoki, Takashi Hisada
  • Publication number: 20220384412
    Abstract: Interconnecting a first chip and a second chip by a bridge member includes a chip handler for handling the first chip and the second chip. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The chip handler has an opening and at least one support surface for supporting the first surfaces of the first chip and the second chip when the first chip and the second chip are mounted to the chip handler. A chip support member supports the first chip and the second chip from the second surfaces, and a bridge handler is provided for inserting the bridge member through the opening of the chip handler and for placing the bridge member onto the first sets of terminals of the first chip and the second chip.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 1, 2022
    Inventors: Akihiro Horibe, Takahito Watanabe, Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori
  • Publication number: 20220193805
    Abstract: An injection apparatus for injection material is disclosed. The injection apparatus includes a tank for storing material. The injection apparatus further includes a head body that has a surface for contacting a substrate and an opening part opened at the surface for discharging the material in fluid-communication with the tank. The injection apparatus further includes a member connected to the opening part, in which the member allows gas to flow into and flow out from the opening part.
    Type: Application
    Filed: March 9, 2022
    Publication date: June 23, 2022
    Inventors: Toyohiro Aoki, Eiji Nakamura, Takashi Hisada
  • Patent number: 11329018
    Abstract: A technique for fabricating a bump structure is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared, in which the pads includes first conductive material. A metallic adhesion layer is coated on each pad. A bump base is formed on each pad by sintering conductive particles using a mold layer, in which the conductive particles includes second conductive material different from the first conductive material.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: May 10, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Hisada, Toyohiro Aoki, Eiji Nakamura
  • Patent number: 11298769
    Abstract: An injection apparatus for injection material is disclosed. The injection apparatus includes a tank for storing material. The injection apparatus further includes a head body that has a surface for contacting a substrate and an opening part opened at the surface for discharging the material in fluid-communication with the tank. The injection apparatus further includes a member connected to the opening part, in which the member allows gas to flow into and flow out from the opening part.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: April 12, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Eiji Nakamura, Takashi Hisada
  • Patent number: 11181704
    Abstract: A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: November 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura, Masao Tokunari
  • Patent number: 11164845
    Abstract: A method for fabricating a resist structure is presented. The method includes preparing a substrate on which plural conductive pads are formed; and patterning a lower resist to form plural lower cavities. The lower resist is deposited above the substrate. Each of the plural lower cavities are located above a corresponding one of the plural conductive pads. Additionally, the method includes patterning an upper resist to form plural upper cavities. The upper resist is deposited on the lower resist. Each of the plural upper cavities are located on a corresponding one of the plural lower cavities and have a diameter larger than a diameter of the corresponding one of the plural lower cavities.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eiji Nakamura, Toyohiro Aoki, Takashi Hisada, Risa Miyazawa
  • Patent number: 11112570
    Abstract: A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: September 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura, Masao Tokunari
  • Publication number: 20210242164
    Abstract: A method for fabricating a resist structure is presented. The method includes preparing a substrate on which plural conductive pads are formed; and patterning a lower resist to form plural lower cavities. The lower resist is deposited above the substrate. Each of the plural lower cavities are located above a corresponding one of the plural conductive pads. Additionally, the method includes patterning an upper resist to form plural upper cavities. The upper resist is deposited on the lower resist. Each of the plural upper cavities are located on a corresponding one of the plural lower cavities and have a diameter larger than a diameter of the corresponding one of the plural lower cavities.
    Type: Application
    Filed: January 30, 2020
    Publication date: August 5, 2021
    Inventors: Eiji Nakamura, Toyohiro Aoki, Takashi Hisada, Risa Miyazawa
  • Publication number: 20210125950
    Abstract: A technique for fabricating a bump structure is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared, in which the pads includes first conductive material. A metallic adhesion layer is coated on each pad. A bump base is formed on each pad by sintering conductive particles using a mold layer, in which the conductive particles includes second conductive material different from the first conductive material.
    Type: Application
    Filed: October 23, 2019
    Publication date: April 29, 2021
    Inventors: Takashi Hisada, Toyohiro Aoki, Eiji Nakamura
  • Patent number: 10991685
    Abstract: A technique of assembling a plurality of chips is disclosed. A plurality of chip layers, each of which includes at least one chip block, is prepared. Each chip block includes a plurality of electrodes assigned the same function. The plurality of the chip layers is sequentially stacked with rotation so as to configure at least one stack of overlapping chip blocks. Each stack holds a plurality of groups of vertically arranged electrodes with shifts in horizontal plane. A through hole is formed, for at least one of the groups, into the plurality of the chip layers at least in part so as to expose electrode surfaces of vertically arranged electrodes in the group. The through hole is filled with conductive material.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: April 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Hisada, Toyohiro Aoki, Eiji Nakamura
  • Patent number: 10930609
    Abstract: A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: February 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura
  • Publication number: 20200361013
    Abstract: An injection apparatus for injection material is disclosed. The injection apparatus includes a tank for storing material. The injection apparatus further includes a head body that has a surface for contacting a substrate and an opening part opened at the surface for discharging the material in fluid-communication with the tank. The injection apparatus further includes a member connected to the opening part, in which the member allows gas to flow into and flow out from the opening part.
    Type: Application
    Filed: May 13, 2019
    Publication date: November 19, 2020
    Inventors: Toyohiro Aoki, Eiji Nakamura, Takashi Hisada
  • Patent number: 10840202
    Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori, Eiji Nakamura, Yasumitsu Orii
  • Patent number: 10833035
    Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori, Eiji Nakamura, Yasumitsu Orii
  • Patent number: 10797011
    Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori, Eiji Nakamura, Yasumitsu Orii
  • Patent number: 10741514
    Abstract: Wafers include a contact pad on a surface of a bulk redistribution layer. A final redistribution layer is formed on the surface and in contact with the contact pad. Solder is formed on the contact pad. The solder includes a pedestal portion formed to a same height as the final redistribution layer and a ball portion above the pedestal portion.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
  • Publication number: 20200227400
    Abstract: A technique of assembling a plurality of chips is disclosed. A plurality of chip layers, each of which includes at least one chip block, is prepared. Each chip block includes a plurality of electrodes assigned the same function. The plurality of the chip layers is sequentially stacked with rotation so as to configure at least one stack of overlapping chip blocks. Each stack holds a plurality of groups of vertically arranged electrodes with shifts in horizontal plane. A through hole is formed, for at least one of the groups, into the plurality of the chip layers at least in part so as to expose electrode surfaces of vertically arranged electrodes in the group. The through hole is filled with conductive material.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 16, 2020
    Inventors: Takashi Hisada, Toyohiro Aoki, Eiji Nakamura