Abstract: A gaming machine of the present invention has a cabinet for housing a gaming unit required for playing a game, a mounting table provided in a housing part for the gaming unit in the cabinet, and an open/close door capable of closing an opening part of the housing part and placed in an upward slant form. The mounting table has such a downward slant structure that it is lower on a back side thereof than on the opening part side.

Abstract: A digital signal processing apparatus for parallel executing a plurality of data processes with a single common command is disclosed, that comprises a plurality of input storing means, each of which is composed of a plurality of storing elements, an input controlling means for controlling the input storing means, a calculating means, having a plurality of element calculating means corresponding to the plurality of the storing elements of the input storing means, for parallel calculating data stored in each storing element of the input storing means, a data storing means, having a plurality of storing elements corresponding to the plurality of element calculating means of the calculating means, for storing calculated result data of the element calculating means corresponding to the storing elements, a plurality of output storing means, each of which is composed of a plurality of storing elements corresponding to the plurality of element calculating means of the calculating means, for storing the calculated res

Abstract: The present invention provides an image processing apparatus and an image processing method. The image processing apparatus includes: a first to a fourth writing FIFO unit and a first to a fourth reading FIFO unit (hereinafter referred to as “FIFO units”) for temporarily retaining image data to write to and read from a data retaining memory; a memory access control unit for performing access to the data retaining memory, the access being requested by the FIFO units; and a writing data control unit for shifting, at all times by a predetermined time, timing of the request made by at least one of the FIFO units to the memory access control unit in comparison with timing of the request made by the other FIFO units to the memory access control unit.

Abstract: A digital signal processing apparatus for parallel executing a plurality of data processes with a single common command is disclosed, that comprises a plurality of input storing means, each of which is composed of a plurality of storing elements, an input controlling means for controlling the input storing means, a calculating means, having a plurality of element calculating means corresponding to the plurality of the storing elements of the input storing means, for parallel calculating data stored in each storing element of the input storing means, a data storing means, having a plurality of storing elements corresponding to the plurality of element calculating means of the calculating means, for storing calculated result data of the element calculating means corresponding to the storing elements, a plurality of output storing means, each of which is composed of a plurality of storing elements corresponding to the plurality of element calculating means of the calculating means, for storing the calculated res