Abstract: According to an embodiment, a non-volatile memory device includes first electrodes arranged in a first direction, a second electrode disposed on a side of the first electrodes in the first direction, a semiconductor layer extending in the first direction through the first electrodes and the second electrode, and a memory film provided between the semiconductor layer and each of the first electrodes. The semiconductor layer includes crystal grains and has a first portion and a second portion, the first portion being adjacent to the first electrodes, and the second portion being adjacent to at least a part of the second electrode, wherein the first portion includes a larger crystal grain than a crystal grain in the second portion.

Abstract: According to an embodiment, a semiconductor device includes two electrodes extending in a first direction, a semiconductor layer provided between the two electrodes, an insulating film disposed between the two electrodes. The two electrodes are arranged in a second direction intersecting the first direction. The semiconductor layer extends in a third direction orthogonal to the first direction and the second direction. The insulating film covers a side surface of the semiconductor layer opposite to one of the two electrodes. The semiconductor layer has a shape in a cross section perpendicular to the third direction such that a width in the first direction at a center of the cross section is narrower than a width, in the first direction, of the side surface.

Abstract: An integrated circuit device according to an embodiment includes an electrode extending in a first direction, two semiconductor members spaced from each other in the first direction and extending in a second direction crossing the first direction, an insulating film placed between each of the two semiconductor members and the electrode and made of a first insulating material, and a first dielectric member placed between the two semiconductor members and made of a second insulating material having a higher permittivity than the first insulating material.

Abstract: An integrated circuit device according to an embodiment includes two electrodes and two semiconductor layers. The two electrodes extend in a first direction. The two semiconductor layers are placed between the two electrodes, are spaced from each other in the first direction, and extend in a second direction orthogonal to the first direction. The two electrodes include extending parts extending out so as to come close to each other. In a cross section orthogonal to the second direction, the extending parts extend into a region interposed between a pair of tangent lines. The pair of tangent lines tangent to both the two semiconductor layers and do not cross each other.

Abstract: According to an embodiment, a semiconductor device includes at least two control electrodes, a plurality of semiconductor layers and an insulating film. Each control electrode extends in a first direction. The semiconductor layers are provided between the control electrodes, and arranged in the first direction. Each semiconductor layer extends in a second direction orthogonal to the first direction. The insulating film covers side surfaces of the semiconductor layers, and is disposed between the control electrodes. Each semiconductor layer has a side surface that includes at least one curved surface swelling in a direction from a center of the semiconductor layer to the insulating film.

Abstract: An integrated circuit device according to an embodiment includes a semiconductor substrate, a first semiconductor member and a second semiconductor member provided on the semiconductor substrate, a first electrode disposed between the first semiconductor member and the second semiconductor member, and a second electrode disposed between the semiconductor substrate and the first electrode. The first semiconductor member and the second semiconductor member extend in a first direction perpendicular to an upper surface of the semiconductor substrate. The first semiconductor member and the second semiconductor member are separated in a second direction orthogonal to the first direction. The first electrode extends in a third direction intersecting both the first direction and the second direction. The second electrode extends in the third direction.

Abstract: An integrated circuit device according to an embodiment, includes a semiconductor member, a first electrode and a second electrode. The semiconductor member includes a first portion of a first conductivity type, a second portion of a second conductivity type, and a third portion of the first conductivity type disposed in this order along a first direction. The first electrode is disposed on a second direction side as viewed from the semiconductor member. The second electrode is disposed on an opposite side of the second direction as viewed from the semiconductor member. An end portion of the second electrode on a first direction side is located in the first direction side rather than that of the first electrode. An end portion of the second electrode on an opposite side of the first direction is located in the first direction side rather than that of the first electrode.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating layers on the substrate, a channel body provided inside a hole piercing the stacked body, and a memory portion provided between the channel body and each of the plurality of electrode layers. The hole has a large diameter portion and a small diameter portion. The diameter of the hole is smaller at the small diameter portion than at the large diameter portion. A thickness of the electrode layer adjacent to the small diameter portion is thicker than a thickness of the electrode layer adjacent to the large diameter portion.

Abstract: A semiconductor device may include a p-channel semiconductor active region and an n-channel semiconductor active region. An element isolation insulating layer electrically isolates the p-channel semiconductor active region from the n-channel semiconductor active region. An insulating layer made of a different material, being in contact with both ends, in its channel length direction, of the p-channel semiconductor active region applies a compression stress in the channel length direction to a channel of the p-channel semiconductor active region. The p-channel semiconductor active region is surrounded by the insulating layer, in the channel length direction, of the p-channel semiconductor active region and by the element isolation insulating layer, parallel to the channel length direction, of the p-channel semiconductor active region. The n-channel semiconductor active region is surrounded by the element isolation insulating layer.

Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer, a second magnetic layer, a non-magnetic layer formed between the first magnetic layer and the second magnetic layer, a charge storage layer having a first surface and a second surface different from the first surface, the first surface facing the second magnetic layer, a first insulating layer formed between the second magnetic layer and the first surface of the charge storage layer, and a second insulating layer formed on the second surface of the charge storage layer.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating layers on the substrate, a channel body provided inside a hole piercing the stacked body, and a memory portion provided between the channel body and each of the plurality of electrode layers. The hole has a large diameter portion and a small diameter portion. The diameter of the hole is smaller at the small diameter portion than at the large diameter portion. A thickness of the electrode layer adjacent to the small diameter portion is thicker than a thickness of the electrode layer adjacent to the large diameter portion.

Abstract: According to one embodiment, a semiconductor storage device includes a first insulating film formed on a substrate and functioning as a FN (Fowler-Nordheim) tunnel film, a first floating gate formed on the first insulating film, an inter-floating-gate insulating layer formed on the first floating gate and functioning as a FN tunnel film, a second floating gate formed on the inter-floating-gate insulating layer, a second insulating film formed on the second floating gate, and a control gate formed on the second insulating film. The inter-floating-gate insulating layer includes a third insulating film and a fourth insulating film having a charge trap property which are stacked.

Abstract: According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: a contact region; a select gate region; and a memory cell region; a first element isolation region formed in the contact region and having a first depth; a second element isolation region formed in the select gate region and having a second depth; and a third element isolation region formed in the memory cell region and having a third depth which is smaller than the first depth.

Abstract: According to an embodiment, a non-volatile semiconductor storage device includes a silicon substrate including an active region isolated by an element isolation insulating film, a first insulating film formed on the active region, a charge accumulation layer formed on the first insulating film, a second insulating film formed on the charge accumulation layer, and a control gate formed on the second insulating film. A plane of the active region being in contact with the element isolation insulating film is a (100) plane or a plane inclining from the (100) plane by an inclination angle of 5° or less.

Abstract: In one embodiment, a non-volatile semiconductor storage device includes a memory cell array in which a plurality of non-volatile memory cells is aligned, and a control unit which repeats a write operation of applying a write voltage to a selected memory cell, a verify operation of checking whether or not data write is completed, and a step-up operation of stepping up the write voltage by an amount of a predetermined step-up voltage when the data write is not completed. Upon the write operation, the control unit applies a first transfer voltage, a voltage value of which is lower than the write voltage, to a first unselected memory cell which is adjacent to the selected memory cell, and applies a second transfer voltage, a voltage value of which is lower than the first transfer voltage, to a second unselected memory cell which is not adjacent to the selected memory cell.

Abstract: According to one embodiment, there is provided a nonvolatile semiconductor memory device including a substrate, a laminated film which has a configuration where first insulating layers and first electrode layers are alternately laminated in a first direction vertical to the substrate, a second insulating layer formed on an inner wall of a first through hole pierced in the first insulating layers and the first electrode layers along the first direction, an intermediate layer formed on a surface of the second insulating layer, a third insulating layer formed on a surface of the intermediate layer, and a pillar-like first semiconductor region which is formed on a surface of the third insulating layer and extends along the first direction.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, made of polysilicon containing a p-type impurity as a group XIII element, and having a lower film and an upper film stacked on the lower film, an inter-electrode insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film. One of a concentration and an activation concentration of the p-type impurity in the upper film is higher than one of a concentration and an activation concentration of the p-type impurity in the lower film.

Abstract: According to one embodiment, a semiconductor storage device includes a first insulating film formed on a substrate and functioning as a FN (Fowler-Nordheim) tunnel film, a first floating gate formed on the first insulating film, an inter-floating-gate insulating layer formed on the first floating gate and functioning as a FN tunnel film, a second floating gate formed on the inter-floating-gate insulating layer, a second insulating film formed on the second floating gate, and a control gate formed on the second insulating film. The inter-floating-gate insulating layer includes a third insulating film and a fourth insulating film having a charge trap property which are stacked.

Abstract: According to one embodiment, a semiconductor device includes an element region partitioned by an isolation region in a semiconductor substrate, and a source region and a drain region formed in a surface layer of the element region by being isolated by a gate trench along a predetermined direction across the element region. The semiconductor device includes a gate electrode formed to reach a position deeper than the source region and the drain region by embedding at least part thereof in the gate trench with a gate dielectric film interposed therebetween. An interface in the drain region, which is in contact with the gate dielectric film, includes a projection projecting toward the gate electrode side.

Abstract: In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.