Patents by Inventor Takashi Karashima
Takashi Karashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230352382Abstract: A wiring substrate includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third conductive layer, a third insulating layer, and a fourth conductive layer. Given that an occupancy ratio of a first conductive pattern in the first conductive layer is a first occupancy ratio, an occupancy ratio of a second conductive pattern in the second conductive layer is a second occupancy ratio, an occupancy ratio of a third conductive pattern in the third conductive layer is a third occupancy ratio, and an occupancy ratio of a fourth conductive pattern in the fourth conductive layer is a fourth occupancy ratio, each of the first occupancy ratio and the third occupancy ratio is greater than each of the second occupancy ratio and the fourth occupancy ratio.Type: ApplicationFiled: February 17, 2023Publication date: November 2, 2023Inventor: Takashi KARASHIMA
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Patent number: 10950686Abstract: The terminal pattern TP1 of the wiring substrate PB has a side T1a facing the terminal pattern TP2 and the terminal pattern TP2 of the wiring substrate PB has a side T2a facing the side T1a of the terminal pattern TP1. The side T1a and the side of T2a are exposed from the opening portion OP1 and OP2 of the solder resist layer SR1 respectively, and outer peripheries of terminal patterns TP1 and TP2 other than sides T1a and T2a are not exposed from opening portions OP1 and OP2. The opening portion OP1 and the opening portion OP2 are separated from each other. The electrode E1 of the capacitor C1 is soldered to the terminal pattern TP1 exposed from the opening portion OP1, and the electrode E2 of the capacitor C1 is soldered to the terminal pattern TP2 exposed from the opening portion OP2.Type: GrantFiled: May 6, 2019Date of Patent: March 16, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Takashi Karashima
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Publication number: 20190363157Abstract: The terminal pattern TP1 of the wiring substrate PB has a side T1a facing the terminal pattern TP2 and the terminal pattern TP2 of the wiring substrate PB has a side T2a facing the side T1a of the terminal pattern TP1. The side T1a and the side of T2a are exposed from the opening portion OP1 and OP2 of the solder resist layer SR1 respectively, and outer peripheries of terminal patterns TP1 and TP2 other than sides T1a and T2a are not exposed from opening portions OP1 and OP2. The opening portion OP1 and the opening portion OP2 are separated from each other. The electrode E1 of the capacitor C1 is soldered to the terminal pattern TP1 exposed from the opening portion OP1, and the electrode E2 of the capacitor C1 is soldered to the terminal pattern TP2 exposed from the opening portion OP2.Type: ApplicationFiled: May 6, 2019Publication date: November 28, 2019Inventor: Takashi KARASHIMA
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Patent number: 9728487Abstract: An object of the present invention is to improve the reliability of a semiconductor device having an imaging function. A semiconductor device includes a package having a cavity and terminals (TE1), a semiconductor chip that has an imaging unit and is arranged in the cavity, and a cap material with which the cavity is sealed and which has translucency. In addition, the semiconductor device includes a mounting board that has a through-hole and terminals (TE2) and is arranged so as to electrically couple the terminals (TE1) to the terminals (TE2), a heat transfer member that is inserted into the through-hole and is coupled to the package, and a heat sink coupled to the heat transfer member.Type: GrantFiled: April 9, 2016Date of Patent: August 8, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Karashima, Yumi Imamura, Yosuke Imazeki
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Publication number: 20160343755Abstract: An object of the present invention is to improve the reliability of a semiconductor device having an imaging function. A semiconductor device includes a package having a cavity and terminals (TE1), a semiconductor chip that has an imaging unit and is arranged in the cavity, and a cap material with which the cavity is sealed and which has translucency. In addition, the semiconductor device includes a mounting board that has a through-hole and terminals (TE2) and is arranged so as to electrically couple the terminals (TE1) to the terminals (TE2), a heat transfer member that is inserted into the through-hole and is coupled to the package, and a heat sink coupled to the heat transfer member.Type: ApplicationFiled: April 9, 2016Publication date: November 24, 2016Inventors: Takashi KARASHIMA, Yumi Imamura, Yosuke Imazeki
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Patent number: 8605277Abstract: Reliability of a semiconductor device is improved. In a flatness inspection of BGA (semiconductor device), there is formed a flatness standard where a permissible range in the direction of (+) of flatness at normal temperature is smaller than a permissible range in the direction of (?). With use of the above flatness standard, a flatness inspection of the semiconductor device at normal temperature is performed to determine whether the mounted item is non-defective or defective. With the above process, defective mounting caused by a package warp when heated during reflow soldering etc. is reduced and reliability of BGA is improved. At the same time, flatness management of a substrate-type semiconductor device with better consideration of a mounting state can be performed.Type: GrantFiled: September 24, 2011Date of Patent: December 10, 2013Assignee: Renesas Electronics CorporationInventors: Satoshi Yamada, Takashi Karashima, Kenya Hironaga, Masatoshi Yasunaga, Yuji Fujimoto
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Patent number: 8580620Abstract: To aim at improvement of reliability of a semiconductor device of flip chip connection type. In assembling a BGA of flip chip connection type, when a semiconductor chip is solder-connected by a flip chip connection, because solder precoat is formed on the surface of a land on the side of an undersurface of a wiring substrate, the connection between the land and a solder ball, which is an external terminal, is solder-connection, and therefore, it is possible to increase impact resistance of a connection part between the land and the solder ball and to aim at improvement of reliability of the BGA.Type: GrantFiled: August 10, 2010Date of Patent: November 12, 2013Assignee: Renesas Electronics CorporationInventors: Kazuyuki Nakagawa, Shinji Baba, Satoshi Yamada, Takashi Karashima
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Publication number: 20120081702Abstract: Reliability of a semiconductor device is improved. In a flatness inspection of BGA (semiconductor device), there is formed a flatness standard where a permissible range in the direction of (+) of flatness at normal temperature is smaller than a permissible range in the direction of (?). With use of the above flatness standard, a flatness inspection of the semiconductor device at normal temperature is performed to determine whether the mounted item is non-defective or defective. With the above process, defective mounting caused by a package warp when heated during reflow soldering etc. is reduced and reliability of BGA is improved. At the same time, flatness management of a substrate-type semiconductor device with better consideration of a mounting state can be performed.Type: ApplicationFiled: September 24, 2011Publication date: April 5, 2012Inventors: Satoshi YAMADA, Takashi KARASHIMA, Kenya HIRONAGA, Masatoshi YASUNAGA, Yuji FUJIMOTO
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Publication number: 20110039375Abstract: To aim at improvement of reliability of a semiconductor device of flip chip connection type. In assembling a BGA of flip chip connection type, when a semiconductor chip is solder-connected by a flip chip connection, because solder precoat is formed on the surface of a land on the side of an undersurface of a wiring substrate, the connection between the land and a solder ball, which is an external terminal, is solder-connection, and therefore, it is possible to increase impact resistance of a connection part between the land and the solder ball and to aim at improvement of reliability of the BGA.Type: ApplicationFiled: August 10, 2010Publication date: February 17, 2011Inventors: Kazuyuki Nakagawa, Shinji Baba, Satoshi Yamada, Takashi Karashima
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Patent number: D584545Type: GrantFiled: April 16, 2008Date of Patent: January 13, 2009Assignee: Okamura CorporationInventors: Takashi Karashima, Hidetaka Sekikawa
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Patent number: D590185Type: GrantFiled: April 16, 2008Date of Patent: April 14, 2009Assignee: Okamura CorporationInventor: Takashi Karashima
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Patent number: D734220Type: GrantFiled: March 11, 2014Date of Patent: July 14, 2015Assignee: Okamura CorporationInventors: Hiroshi Saotome, Takashi Karashima
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Patent number: D762876Type: GrantFiled: March 31, 2015Date of Patent: August 2, 2016Assignee: Okamura CorporationInventor: Takashi Karashima