Abstract: A vehicular power supply device to be equipped in a vehicle includes an electric storage unit group, an inverter, a driving motor, a converter, an electric device group, a first switch, and a second switch. The electric storage unit group includes first and second electric storage units. The driving motor is to be coupled to the electric storage unit group via the inverter. The electric device group is to be coupled to the electric storage unit group via the converter. The first switch is to be controlled between a state where the first electric storage unit is coupled to the inverter and a state where the first electric storage unit is coupled to the converter. The second switch is to be controlled between a state where the second electric storage unit is coupled to the inverter and a state where the second electric storage unit is coupled to the converter.

Abstract: A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.

Abstract: Disclosed are an image processing device and an image processing method which achieve an increase in the speed of image processing by designating and operating a plurality of image processing units each corresponding to a specific function for the image processing in accordance with a program. A frame memory (21 . . . ) stores image data to be processed. Parallel memories (121 . . . ) each receive all or part of the image data stored in the frame memory (21 . . . ) and transmit the received image data to any of DMACs (111 . . . ) or processing units (13A . . . ) for the image processing. The processing units (13A . . . ) each have a function corresponding to a function for the image processing. The processing units (13A . . . ) each receive all or part of the image data from the parallel memory (121 . . . ) or the frame memory (21 . . . ) in accordance with a command from a CPU (3) and perform processing based on the function for the image processing on all or part of the image data.

Abstract: A semiconductor integrated circuit device is provided which has a plurality of photo detector circuits and a plurality of processing elements. Each of the photo detector circuits includes a comparing circuit, which compares an output of a photo detector element with a reference voltage. A/D conversion is performed by counting the elapsed time until the output of the photo detector element drops below the reference voltage, and a level of the reference voltage as a function of time to be applied to the comparing circuit and time intervals of the counting are uniquely determined based on given quantization intervals of an amount of current generated by the photo detector element. In addition, the photo detector elements may be reset locally based on the result of the corresponding processing element.

Abstract: A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.

Abstract: An image detection processor of the present invention enhances the processing speed of the calculation of the center of gravity or the like of a target with a simple constitution. The image detection processor arranges a plurality of image detection processing elements 1-1 to 1-64 on a plane. Each image detection processing element includes an adder circuit 15 which converts an output of a photoelectric conversion part 5 into digital signals and can receive the digital signals as an input in a matrix form. Cumulative adders are constituted by connecting the adder circuits 15 for respective rows. Series adders 2-1 to 2-8 which are connected in series respectively receive outputs of final stages of cumulative adders of respective rows as inputs and can cumulatively add these outputs.

Abstract: A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.

Abstract: A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.

Abstract: A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.

Abstract: An image detection processor of the present invention enhances the processing speed of the calculation of the center of gravity or the like of a target with a simple constitution. The image detection processor arranges a plurality of image detection processing elements 1-1 to 1-64 on a plane. Each image detection processing element includes an adder circuit 15 which converts an output of a photoelectric conversion part 5 into digital signals and can receive the digital signals as an input in a matrix form. Cumulative adders are constituted by connecting the adder circuits 15 for respective rows. Series adders 2-1 to 2-8 which are connected in series respectively receive outputs of final stages of cumulative adders of respective rows as inputs and can cumulatively add these outputs.