Abstract: A discharge waveform generating device includes a timing reference generation circuit, a timing adjustment circuit, a waveform pattern generation circuit, and a timing correction circuit. The timing reference generation circuit generates a discharge timing for generating, from image data, a discharge waveform of ink to print the image data, based on a line synchronization signal for synchronizing discharge operations of discharge nozzles to discharge ink. The timing adjustment circuit sets an adjustment value of the discharge timing. The waveform pattern generation circuit generates the waveform from the image data, based on outputs of the timing reference generation circuit and the timing adjustment circuit.

Abstract: A discharge waveform generating device includes a timing reference generation circuit, a timing adjustment circuit, a waveform pattern generation circuit, and a timing correction circuit. The timing reference generation circuit generates a discharge timing for generating, from image data, a discharge waveform of ink to print the image data, based on a line synchronization signal for synchronizing discharge operations of discharge nozzles to discharge ink. The timing adjustment circuit sets an adjustment value of the discharge timing. The waveform pattern generation circuit generates the waveform from the image data, based on outputs of the timing reference generation circuit and the timing adjustment circuit.

Abstract: A light emission element array chip includes light emission light groups each of which includes N light emission elements arranged in a sub-scanning direction. The light emission light groups include a first block of the light emission element groups arranged at intervals of a first predetermined distance in a main-scanning direction. The light emission light groups further include a second block of one or more of the light emission element groups at either end side of the light emission element array chip shifted from a position of each light emission element group included in the first block of the light emission element groups by a second predetermined distance in the sub-scanning direction.

Abstract: An exposure device, which emits light according to a gray level of image data, includes plural light emitting element lines arranged at different positions in a sub scanning direction, a number of the light emitting element lines being a number of bits representing a number of gray levels. Each of the light emitting element lines includes plural light emitting elements arranged in a line in a direction parallel to a main scanning direction, the light emitting elements numbers of layers of organic electro-luminescence light emitting elements being the same. The numbers of layers of the organic electro-luminescence light emitting elements laminated in the light emitting element lines, which are arranged at different positions in the sub scanning direction, are different from each other.

Abstract: A PWM signal generating circuit, printer, and PWM signal generating method are described. The PWM signal generating circuit includes: a single counter configured to count values expressed in N bits; and at least one arithmetic device configured to generate a PWM signal, each of the at least one arithmetic device including a pulse width data storage unit for storing N-bit pulse width data representing a pulse width of the PWM signal to be generated, and an adder for calculating a carry value from a most significant bit obtained when adding the count value and the pulse width data. A signal having a level corresponding to the carry value is output at every change in the count value so that the PWM signal having the pulse width of the pulse width data is generated.

Abstract: An exposure device, which emits light according to a gray level of image data, includes plural light emitting element lines arranged at different positions in a sub scanning direction, a number of the light emitting element lines being a number of bits representing a number of gray levels. Each of the light emitting element lines includes plural light emitting elements arranged in a line in a direction parallel to a main scanning direction, the light emitting elements numbers of layers of organic electro-luminescence light emitting elements being the same. The numbers of layers of the organic electro-luminescence light emitting elements laminated in the light emitting element lines, which are arranged at different positions in the sub scanning direction, are different from each other.

Abstract: A PWM signal generating circuit, printer, and PWM signal generating method are described. The PWM signal generating circuit includes: a single counter configured to count values expressed in N bits; and at least one arithmetic device configured to generate a PWM signal, each of the at least one arithmetic device including a pulse width data storage unit for storing N-bit pulse width data representing a pulse width of the PWM signal to be generated, and an adder for calculating a carry value from a most significant bit obtained when adding the count value and the pulse width data. A signal having a level corresponding to the carry value is output at every change in the count value so that the PWM signal having the pulse width of the pulse width data is generated.

Abstract: The oscillating circuit (100) includes a variable frequency oscillating circuit (10) for generating a clock signal (CK) whose frequency increases in response to an up-signal (UP) and decreases in response to a down-signal (DOWN), the frequency going up and down continuously between an upper-limit frequency and a lower-limit frequency. An up/down control circuit (20) outputs the down-signal when a duration of a low level of the clock signal drops below a first delay time and outputs the up-signal when the duration exceeds a second delay time longer than the first delay time.

Abstract: An oscillation frequency control circuit configured to control a frequency of a second clock signal of an oscillation circuit generating and outputting the second clock signal having a frequency in response to an input control signal is disclosed. The oscillation frequency control circuit includes a frequency difference detection circuit unit configured to detect a difference between a frequency of a predetermined first clock signal input externally and the frequency of the second clock signal, and generate and output a signal indicating a result of the detection; and a frequency control circuit unit configured to control the frequency of the second clock signal so that the frequency of the second clock signal continually changes back and forth between a predetermined lower limit value and a predetermined upper limit value in response to the output signal from the frequency difference detection circuit.

Abstract: An oscillation frequency control circuit controls a second oscillation circuit, which generates and outputs a second clock signal of a second frequency according to a received control signal, to control the second frequency. The oscillation frequency control circuit includes a frequency difference detection circuit unit configured to detect a difference between a predetermined first frequency of a first clock signal generated by an external first oscillation circuit and the second frequency, and generate and output an output signal indicating a detection result, and a frequency control circuit unit configured to control, according to the output signal of the frequency difference detection circuit unit, the second oscillation circuit to control the second frequency of the second clock signal to make an absolute value of the difference between the first frequency and the second frequency greater than a predetermined value.

Abstract: The oscillating circuit (100) includes a variable frequency oscillating circuit (10) for generating a clock signal (CK) whose frequency increases in response to an up-signal (UP) and decreases in response to a down-signal (DOWN), the frequency going up and down continuously between an upper-limit frequency and a lower-limit frequency. An up/down control circuit (20) outputs the down-signal when a duration of a low level of the clock signal drops below a first delay time and outputs the up-signal when the duration exceeds a second delay time longer than the first delay time.

Abstract: An oscillation frequency control circuit configured to control a frequency of a second clock signal of an oscillation circuit generating and outputting the second clock signal having a frequency in response to an input control signal is disclosed. The oscillation frequency control circuit includes a frequency difference detection circuit unit configured to detect a difference between a frequency of a predetermined first clock signal input externally and the frequency of the second clock signal, and generate and output a signal indicating a result of the detection; and a frequency control circuit unit configured to control the frequency of the second clock signal so that the frequency of the second clock signal continually changes back and forth between a predetermined lower limit value and a predetermined upper limit value in response to the output signal from the frequency difference detection circuit.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a digital audio circuit which converts an input digital signal into an analog audio signal, a DC-DC converter having a switching power source circuit, and an audible frequency determining circuit. In order that a difference between a frequency of a first clock signal for digital to analog conversion which is used in the digital audio circuit and a frequency of a second clock signal for switching control which is used in a DC-DC converter exceeds a maximum audible frequency, a frequency comparing circuit in the audible frequency determining circuit outputs a signal to a frequency changing circuit in the DC-DC converter. The frequency changing circuit causes a second oscillating circuit to change the second frequency.

Abstract: A noise canceller configured to remove surrounding noise from a desirable sound collected by a first microphone, the noise canceller includes a second microphone arranged in a place separated from the first microphone and configured to collect the surrounding noise; a second amplifier circuit part configured to amplify an output signal of the second microphone and output the output signal; and a signal processing circuit part configured to remove the surrounding noise from a sound collected by the first microphone by using the output signal of the second amplifier circuit part. The second amplifier circuit part is provided in the vicinity of the second microphone.

Abstract: In a color video signal processing method, color difference component signals are converted into RGB component signals by a digital to digital conversion so as to reduce a size of a processing unit used for the conversion. An analog composite signal is converted into analog color difference component signals. The analog color difference component signals are then converted into digital color difference component signals. The digital color difference component signals are converted into digital RGB component signals by a digital to digital conversion based on an approximation method. Finally, the digital RGB component signals are converted into analog RGB component signals. The digital-to-digital conversion may be performed in accordance with equations in which each factor is a fractional number having a denominator of a power of 2.

Abstract: The present invention provides a processing system capable of displaying images on a screen and moving the images on the screen in response to for example user input. The system displays images on, for example, a computer monitor or a video game monitor using an image display apparatus that includes a background screen control portion that provides image data for one or more background screens and which is capable of performing horizontal and vertical scrolling functions.