Patents by Inventor Takashi Nakamoto
Takashi Nakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10549460Abstract: Upon manufacturing a heat-resistant container using PET sheet, high heat-resistance is achieved without a stretching operation. The method comprises a molding sheet-making process, wherein a sheet is made including organic acid metal salt particulates produced by allowing an inorganic basic material or carbonate that is solid at ordinary temperature to react with an organic acid that is solid at ordinary temperature in the equivalent relationship, and a container-molding process, wherein, the molding sheet made in the molding sheet-making process is heated to 80-130° C., formed into a container shape by a vacuum or vacuum-pressure forming machine using a mold, and heat-set by keeping at 130-220° C. in the same mold, and the container formed in the container-molding process has a crystallinity of 18% or more.Type: GrantFiled: March 22, 2017Date of Patent: February 4, 2020Assignee: NAKAMOTO PACKS CO., LTD.Inventors: Takashi Nakamoto, Hitoshi Sasaki, Kaori Shimizu
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Publication number: 20170274567Abstract: Upon manufacturing a heat-resistant container using PET sheet, high heat-resistance is achieved without a stretching operation. The method comprises a molding sheet-making process, wherein a sheet is made including organic acid metal salt particulates produced by allowing an inorganic basic material or carbonate that is solid at ordinary temperature to react with an organic acid that is solid at ordinary temperature in the equivalent relationship, and a container-molding process, wherein, the molding sheet made in the molding sheet-making process is heated to 80-130° C., formed into a container shape by a vacuum or vacuum-pressure forming machine using a mold, and heat-set by keeping at 130-220° C. in the same mold, and the container formed in the container-molding process has a crystallinity of 18% or more.Type: ApplicationFiled: March 22, 2017Publication date: September 28, 2017Applicant: NAKAMOTO PACKS CO., LTD.Inventors: Takashi NAKAMOTO, Hitoshi SASAKI, Kaori SHIMIZU
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Patent number: 9365423Abstract: The system includes adsorbent-packed towers 11 and 21 filled with H2S adsorbent which triethanolamine is supported by activated carbon. Mixed gas derived from a synthesis gas containing CO2 and H2S at about 40° C. is supplied to the adsorbent-packed towers 11 and 21 through a line. Valves 12 and 13 are opened, valves 22 and 23 are closed, valves 14 and 15 are closed, and valves 24 and 25 are opened to perform adsorption of H2S contained in the gas to be treated in the adsorbent-packed tower 11 in a dry state and to perform desorption of H2S in the adsorbent-packed tower 21. When adsorption of H2S contained in the gas to be treated is performed in the adsorbent-packed tower 21 and desorption of H2S is performed in the adsorbent-packed tower 11, the valves 12, 13, 24, and 25 are closed and the valves 22, 23, 14, and 15 are opened.Type: GrantFiled: October 29, 2012Date of Patent: June 14, 2016Assignee: KAWASAKI JUKOGYO KABUSHIKI KAISHAInventors: Takashi Nakamoto, Toshinori Muraoka, Shigenobu Okajima, Norihiko Kumada, Masatoshi Hirokawa, Takatoshi Shoji
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Publication number: 20140360368Abstract: The system includes adsorbent-packed towers 11 and 21 filled with H2S adsorbent which triethanolamine is supported by activated carbon. Mixed gas derived from a synthesis gas containing CO2 and H2S at about 40° C. is supplied to the adsorbent-packed towers 11 and 21 through a line. Valves 12 and 13 are opened, valves 22 and 23 are closed, valves 14 and 15 are closed, and valves 24 and 25 are opened to perform adsorption of H2S contained in the gas to be treated in the adsorbent-packed tower 11 in a dry state and to perform desorption of H2S in the adsorbent-packed tower 21. When adsorption of H2S contained in the gas to be treated is performed in the adsorbent-packed tower 21 and desorption of H2S is performed in the adsorbent-packed tower 11, the valves 12, 13, 24, and 25 are closed and the valves 22, 23, 14, and 15 are opened.Type: ApplicationFiled: October 29, 2012Publication date: December 11, 2014Inventors: Takashi Nakamoto, Toshinori Muraoka, Shigenobu Okajima, Norihiko Kumada, Masatoshi Hirokawa, Takatoshi Shoji
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Patent number: 7993569Abstract: The present invention provides a method of manufacturing high-melting-tension heat-resistant transparent or opaque sheets, boards, and molds from polyethylene terephthalate (PET). The method is characterized in that a mixture of: (1) PET polyester whose melt flow rate (MFR) is 45-130 g/10 minutes (a); (2) coupling agent master batch (f) comprising coupling agent (d) and substrate (e), wherein coupling agent (d) is a mixture of compounds containing 2 epoxy groups (b) and compounds containing 3 or more epoxy groups (c); and (3) catalyst master batch (i) comprising coupling reaction catalyst (g) and substrate (h); is melted in a reaction-extruder to give PET polyester whose MFR is 40 g/10 minutes or less.Type: GrantFiled: August 27, 2004Date of Patent: August 9, 2011Assignees: FTEX, Incorporated, Nakamoto Packs Co., Ltd.Inventors: Yukio Kobayashi, Takashi Fujimaki, Takashi Nakamoto
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Patent number: 7916921Abstract: It can be enabled an accurate diagnosis of osteoporosis by a simple method utilizing panoramic radiographs without requiring special skill or experience of a technician engaged in diagnosis of osteoporosis.Type: GrantFiled: October 18, 2005Date of Patent: March 29, 2011Assignee: Hiroshima University Independent Administrative AgencyInventors: Akira Asano, Akira Taguchi, Takashi Nakamoto, Keiji Tanimoto, Zainal Arifin Agus
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Patent number: 7602955Abstract: The present invention provides an osteoporosis diagnosis aiding apparatus that utilizes a panoramic radiograph. A digitalized image of the panoramic radiograph enters a personal computer (S210). The cortical bone at the lower edge of the mandibular molar in the panoramic radiograph is specified with a mouse to make that part a target of examination (S220). This extracted image is subjected to the following image processing. (1) Subject the image to median filtering so as to reduce noises throughout that image. (2) Find a skeleton constituted by micro-structural elements (S230). (3) Extract only components parallel to the tilt of the lower edge of the mandible (S240). (4) Binarize the image using Otsu's linear discrimination method, for example (S250). The binarized lines are then classified into three groups according to size, and can be determined as a risk of osteoporosis in a case where there is more than just a single line classified in the largest line group aside from the smallest line group.Type: GrantFiled: December 25, 2003Date of Patent: October 13, 2009Assignee: Japan Science and Technology AgencyInventors: Akira Taguchi, Takashi Nakamoto, Akira Asano
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Publication number: 20070286467Abstract: It can be enabled an accurate diagnosis of osteoporosis by a simple method utilizing panoramic radiographs without requiring special skill or experience of a technician engaged in diagnosis of osteoporosis.Type: ApplicationFiled: October 18, 2005Publication date: December 13, 2007Applicant: HIROSHIMA UNIVERSITYInventors: Akira Asano, Akira Taguchi, Takashi Nakamoto, Kenji Tanimoto, Zainal Agus
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Publication number: 20070052131Abstract: A PET-based polyester packaging film capable of weld-cut sealing and heat-shrinkage refers to a film obtained by biaxially orienting a material prepared through block copolymerization of a PET/PETG/polyester elastomer with an epoxy resin and a catalyst. This film eliminates the most serious weak points in physical properties of conventional PET films, and is useful for packaging of books, bottlesets, food containers, etc., for general packaging, packaging of industrial materials, and the like, and is further useful in the field of packing and packaging of daily commodities, civil engineering and construction members, electric and electronic members, and automobile vehicle members, etc. Moreover, this film can be produced through effective use of the huge amount of recycled PET bottles and inexpensive PET for fiber as a prepolymer, and thus is also highly beneficial socially.Type: ApplicationFiled: September 21, 2004Publication date: March 8, 2007Applicant: NAKAMOTO PACKS CO., LTD.Inventors: Takashi Fujimaki, Yukio Kobayashi, Takashi Nakamoto, Hiroshi Shibano
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Publication number: 20060239532Abstract: The present invention provides an osteoporosis diagnosis aiding apparatus that utilizes a panoramic radiograph. A digitalized image of the panoramic radiograph enters a personal computer (S210). The cortical bone at the lower edge of the mandibular molar in the panoramic radiograph is specified with a mouse to make that part a target of examination (S220). This extracted image is subjected to the following image processing. (1) Subject the image to median filtering so as to reduce noises throughout that image. (2) Find a skeleton constituted by micro-structural elements (S230). (3) Extract only components parallel to the tilt of the lower edge of the mandible (S240). (4) Binarize the image using Otsu's linear discrimination method, for example (S250). The binarized lines are then classified into three groups according to size, and can be determined as a risk of osteoporosis in a case where there is more than just a single line classified in the largest line group aside from the smallest line group.Type: ApplicationFiled: December 25, 2003Publication date: October 26, 2006Inventors: Akira Taguchi, Takashi Nakamoto, Akira Asano
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Publication number: 20060043646Abstract: The present invention provides a method of manufacturing high-melting-tension heat-resistant transparent or opaque sheets, boards, and moulds from polyethylene terephthalate (PET). The method is characterised in that a mixture of: (1) PET polyester whose melt flow rate (MFR) is 45-130 g/10 minutes (a); (2) coupling agent master batch (f) comprising coupling agent (d) and substrate (e), wherein coupling agent (d) is a mixture of compounds containing 2 epoxy groups (b) and compounds containing 3 or more epoxy groups (c); and (3) catalyst master batch (i) comprising coupling reaction catalyst (g) and substrate (h); is melted in a reaction-extruder to give PET polyester whose MFR is 40 g/10 minutes or less.Type: ApplicationFiled: August 27, 2004Publication date: March 2, 2006Inventors: Yukio Kobayashi, Takashi Fujimaki, Takashi Nakamoto
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Patent number: 6889274Abstract: A signal processing circuit having a data input-output (I/O) circuit, a microprocessor, a dedicated processing circuit, a local memory, and a memory access control circuit interconnected over a bus. The system bus connects to the data I/O circuit, microprocessor, dedicated processing circuit, and memory access control circuit. A local memory bus connects to the local memory. First, second, and third connection circuits connect between the system bus and local memory bus, between a first local bus in the dedicated processing circuit and the local memory bus, and between a second local bus in the data I/O circuit and the local memory bus. The memory access control circuit controls the first, second, and third connection circuits according to priorities assigned for the connection circuits and determines which of the second local bus, first local bus, and system bus will be connected to the local memory bus.Type: GrantFiled: June 1, 2001Date of Patent: May 3, 2005Assignee: Renesas Technology Corporation.Inventors: Hiromi Watanabe, Takashi Nakamoto, Hiroshi Hatae, Junko Haruta, Masaru Hase, Kenichi Iwata, Hiroshi Yamada, Yutaka Okada
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Publication number: 20040225815Abstract: The invention incorporates a signal processing circuit having a data input-output (I/O) circuit, a microprocessor, a dedicated processing circuit, a local memory, and a memory access control circuit interconnected over a bus. The bus includes a system bus and a local memory bus. The system bus connects to the data I/O circuit, microprocessor, dedicated processing circuit, and memory access control circuit. The local memory bus connects to the local memory. First, second, and third connection circuits connect between the system bus and local memory bus, between a first local bus in the dedicated processing circuit and the local memory bus, and between a second local bus in the data I/O circuit and the local memory bus. The memory access control circuit controls the first, second, and third connection circuits according to priorities assigned for the connection circuits. The system bus transfers control information among the data I/O circuit, dedicated processing circuit, and memory access control.Type: ApplicationFiled: June 1, 2001Publication date: November 11, 2004Applicant: Hitachi, Ltd.Inventors: Hiromi Watanabe, Takashi Nakamoto, Hiroshi Hatae, Junko Haruta, Masaru Hase, Kenichi Iwata, Hiroshi Yamada, Yutaka Okada
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Patent number: 6675183Abstract: There is provided a filtering circuit whose circuit scale is small and which is suitable for a digital data string in which data of luminance signals Y and color-difference signals Cb and Cr are regularly inserted or multiplexed. The digital filtering circuit comprises a delay line composed of a plurality of D flip-flops which is operative with frequency of the data string in which the luminance signals Y and the color-difference signals Cb and Cr are regularly inserted or multiplexed a plurality of multipliers for multiplying a plurality of taps of the delay line by respective coefficients and an adder for adding outputs of said multipliers, wherein the taps connected to the multipliers is switched by selectors. It allows one digital filtering circuit to be used for processing the signals Y, Cb and Cr in a time division manner to realize the digital filtering circuit which uses less multipliers and adders and whose circuit scale is small.Type: GrantFiled: January 17, 2002Date of Patent: January 6, 2004Assignee: Hitachi, Ltd.Inventors: Junko Nakase, Takashi Nakamoto
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Patent number: 6587901Abstract: The information processing system is configured such that a portable information terminal and host information processing apparatus can connect via a bus. A program executed by a CPU of the portable information terminal is sent from the host information processing apparatus on the bus to the portable information terminal for storage in a volatile memory. Thus, the portable information terminal does not need a non-volatile memory.Type: GrantFiled: November 15, 2001Date of Patent: July 1, 2003Assignee: Hitachi, Ltd.Inventors: Naohiro Nishikawa, Yukako Fujita, Takashi Nakamoto
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Publication number: 20020062413Abstract: An information processing system that in addition to doing away with non-volatile memory of a portable information terminal, is configured such that a portable information terminal and host information processing apparatus can connect via a bus, and a program executed by a CPU of the portable information terminal is sent from the host information processing apparatus on the bus to the portable information terminal for storage in volatile memory.Type: ApplicationFiled: November 15, 2001Publication date: May 23, 2002Inventors: Naohiro Nishikawa, Yukako Fujita, Takashi Nakamoto
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Publication number: 20020059352Abstract: There is provided a filtering circuit whose circuit scale is small and which is suitable for a digital data string in which data of luminance signals Y and color-difference signals Cb and Cr are regularly inserted or multiplexed. The digital filtering circuit comprises a delay line composed of a plurality of D flip-flops which is operative with frequency of the data string in which the luminance signals Y and the color-difference signals Cb and Cr are regularly inserted or multiplexed a plurality of multipliers for multiplying a plurality of taps of the delay line by respective coefficients and an adder for adding outputs of said multipliers, wherein the taps connected to the multipliers is switched by selectors. It allows one digital filtering circuit to be used for processing the signals Y, Cb and Cr in a time division manner to realize the digital filtering circuit which uses less multipliers and adders and whose circuit scale is small.Type: ApplicationFiled: January 17, 2002Publication date: May 16, 2002Applicant: Hitachi, Ltd.Inventors: Junko Nakase, Takashi Nakamoto
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Patent number: 6377968Abstract: There is provided a filtering circuit whose circuit scale is small and which is suitable for a digital data string in which data of luminance signals Y and color-difference signals Cb and Cr are regularly inserted or multiplexed. The digital filtering circuit includes a delay line composed of a plurality of D flip-flops which is operative with frequency of the data string in which the luminance signals Y and the color-difference signals Cb and Cr are regularly inserted or multiplexed a plurality of multipliers for multiplying a plurality of taps of the delay line by respective coefficients and an adder for adding outputs of said multipliers, wherein the taps connected to the multipliers is switched by selectors. It allows one digital filtering circuit to be used for processing the signals Y, Cb and Cr in a time division manner to realize the digital filtering circuit which uses less multipliers and adders and whose circuit scale is small.Type: GrantFiled: April 15, 1999Date of Patent: April 23, 2002Assignee: Hitachi, Ltd.Inventors: Junko Nakase, Takashi Nakamoto
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Patent number: 5731838Abstract: In a moving picture data decoding apparatus, the storage of reference picture data in a picture memory is executed by dividing the picture memory into two memory areas. An address generator generates an address so that the reference picture data adjacent to the division may be doubly written into the two memory areas. As a result, the processing can be effected in a predetermined access time period irrespective of the read-out location.Type: GrantFiled: January 19, 1996Date of Patent: March 24, 1998Assignee: Hitachi, Ltd.Inventors: Hiroshi Gunji, Takashi Nakamoto, Masuo Oku, Yukiko Midorikawa, Hironori Kojima
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Patent number: 5471600Abstract: An address generating circuit includes a latch circuit and two adder/subtractors. The inputs of the first adder/subtractor are from the latch circuit and from a distance relative to a value of a base pointer, and the output computes an address. The second adder/subtractor uses loop width information to adjust the computed address of the first adder/subtractor so that it falls within a loop area.Type: GrantFiled: February 22, 1995Date of Patent: November 28, 1995Assignee: NEC CorporationInventor: Takashi Nakamoto