Abstract: A request change unit outputs a command as a request under control of a judgment control unit. A response condition determination unit determines a condition that is to be matched by a correct response which is to be returned from the other device-in-communication in reply to the command if the other device-in-communication operates in conformity with a protocol. A check unit checks a response received from the other device-in-communication in reply to the command, against the condition. If the received response does not match the condition but is correctable to match the condition as a result of the check, a response correction unit corrects the received response to match the condition under control of the judgment control unit.

Abstract: A multi-processor control device according to an example of the invention comprises a cooperative control unit which determines priorities of requests issued from processors to a shared resource which are used to suppress a total power consumption of the processors within a range in which performance constraints of programs executed by the processors are satisfied, and determines a frequency of each of the processors so as to suppress the total power consumption within the range in which the performance constraint of the each program is satisfied, a first control unit which issues requests from the processors to the shared resource in accordance with priorities determined by the cooperative control unit, and a second control unit which controls the frequency of each of the processors in accordance with the frequency determined by the cooperative control unit.

Abstract: A multi-processor control device according to an example of the invention comprises a cooperative control unit which determines priorities of requests issued from processors to a shared resource which are used to suppress a total power consumption of the processors within a range in which performance constraints of programs executed by the processors are satisfied, and determines a frequency of each of the processors so as to suppress the total power consumption within the range in which the performance constraint of the each program is satisfied, a first control unit which issues requests from the processors to the shared resource in accordance with priorities determined by the cooperative control unit, and a second control unit which controls the frequency of each of the processors in accordance with the frequency determined by the cooperative control unit.

Abstract: A request change unit outputs a command as a request under control of a judgment control unit. A response condition determination unit determines a condition that is to be matched by a correct response which is to be returned from the other device-in-communication in reply to the command if the other device-in-communication operates in conformity with a protocol. A check unit checks a response received from the other device-in-communication in reply to the command, against the condition. If the received response does not match the condition but is correctable to match the condition as a result of the check, a response correction unit corrects the received response to match the condition under control of the judgment control unit.

Abstract: An asynchronous digital system, an asynchronous data path circuit, an asynchronous digital signal processing circuit and an asynchronous digital signal processing method, which enables improved processing speed while maintaining high reliability are provided by dividing the overall chip into blocks with a specified area, forming the connection between the blocks by applying thereto a delay insensitive (Dl) model or a quasi delay insensitive (QDI) model, while forming each block by applying thereto a scalable delay insensitive (SDI) model.

Abstract: An asynchronous digital system, an asynchronous data path circuit, an asynchronous digital signal processing circuit and an synchronous digital signal processing method, which enables improved processing speed while maintaining high reliability are provided by dividing the overall chip into blocks with a specified area, forming the connection between the blocks by applying thereto a delay insensitive (DI) model or a quasi delay insensitive (QDI) model, while forming each block by applying thereto a scalable delay insensitive (SDI) model. In the SDI model, the system is configured using circuit components having a delay assumed during design in which if the specification states that a signal transition (b) in a subcircuit 7 precedes a signal transition (c) in a subcircuit 8, k.multidot.

Abstract: An elementary cell uses single-flux-quanta as two-valued logic propagation signals and is effective for Constructing asynchronous superconducting logic circuits. The elementary cell comprises one OR circuit section and one AND circuit section. Input pulses applied to two input terminals of the elementary cell are split at signal splitting sections in the elementary cell and applied to both inputs of the OR circuit section and both inputs of the AND circuit section. The output of the OR circuit section is defined as the OR output of the elementary cell. A first arrival pulse memory section is provided in the AND circuit section and when one of two input pulses input to the two input terminals of the AND circuit section arrives before the other, this fact is recorded in the first arrival pulse memory section as logical "1".

Abstract: A programmable logic array (PLA) is achieved by taking various EOR sums of programmable AND term generator output signals. The EOR term generator receives externally applied logic constant signals on respective logic constant signal lines. Each logic constant signal line is coupled to the AND term generator outputs by a plurality of EOR elements which are either connected in series and controlled by different AND terms or cascaded in tree-like fashion.

Abstract: An asynchronous arbiter for use in systems where two or more signal sources attempt to simultaneously use a resource operates to insure that signal source requests are honored in the sequence of the earliest generated request to the latest generated request. The arbiter preserves the order of requests while the respective request signals are kept waiting, and an acknowledgement signal for use of the resource is given in succession to the respective signal sources starting from the signal source with the earliest request to successively service the requests of the signal sources. The arbiter is implemented with a competition decision circuit receiving as inputs a plurality of request signals from respective signal sources and providing an output to a control circuit designating the signal source to be serviced.