Patents by Inventor Takashi Ohsumi
Takashi Ohsumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8211750Abstract: A semiconductor device includes a substrate for transmitting light, a wiring layer provided on the substrate, a semiconductor chip formed on the wiring layer, a columnar electrode, a sealant, and an external connection terminal electrically connected to the semiconductor chip via the wiring layer and protruding electrode. The device includes a cut surface formed by dicing and constituted by only the substrate and the sealant. Since the cut surface has a single-layer structure as a result of forming the sealant in a single step, moisture cannot infiltrate through the sealant, hence a device resistant to corrosion and operational defects is provided.Type: GrantFiled: October 30, 2008Date of Patent: July 3, 2012Assignee: Oki Semiconductor Co., Ltd.Inventor: Takashi Ohsumi
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Patent number: 8164164Abstract: A semiconductor wafer has a substrate, and a plurality of active areas formed on the substrate. Integrated circuits are formed in the active areas. The semiconductor wafer also has dicing areas formed between the adjacent active areas. A seal ring is formed along the edge (periphery) of each active area. The semiconductor wafer also has interconnects formed closely to the inside of the seal ring. A protective layer covers the active areas. A protective film is formed on the protective layer at the locations of the active areas. The semiconductor wafer also has other interconnects formed on the protective film for electrical connection to the integrated circuits. Preferably, when the aspect ratio of a groove formed in the protective layer between the seal ring and the interconnect is 0.5 or more, this groove is covered with the protective film.Type: GrantFiled: September 22, 2010Date of Patent: April 24, 2012Assignee: Oki Semiconductor Co., Ltd.Inventor: Takashi Ohsumi
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Patent number: 7915746Abstract: A semiconductor wafer has a substrate, and a plurality of active areas formed on the substrate. Integrated circuits are formed in the active areas. The semiconductor wafer also has dicing areas formed between the adjacent active areas. A seal ring is formed along the edge (periphery) of each active area. The semiconductor wafer also has interconnects formed closely to the inside of the seal ring. A protective layer covers the active areas. A protective film is formed on the protective layer at the locations of the active areas. The semiconductor wafer also has another interconnects formed on the protective film for electrical connection to the integrated circuits. Preferably, when the aspect ratio of a groove formed in the protective layer between the seal ring and the interconnect is 0.5 or more, this groove is covered with the protective film.Type: GrantFiled: May 26, 2006Date of Patent: March 29, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Takashi Ohsumi
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Publication number: 20110006438Abstract: A semiconductor wafer has a substrate, and a plurality of active areas formed on the substrate. Integrated circuits are formed in the active areas. The semiconductor wafer also has dicing areas formed between the adjacent active areas. A seal ring is formed along the edge (periphery) of each active area. The semiconductor wafer also has interconnects formed closely to the inside of the seal ring. A protective layer covers the active areas. A protective film is formed on the protective layer at the locations of the active areas. The semiconductor wafer also has other interconnects formed on the protective film for electrical connection to the integrated circuits. Preferably, when the aspect ratio of a groove formed in the protective layer between the seal ring and the interconnect is 0.5 or more, this groove is covered with the protective film.Type: ApplicationFiled: September 22, 2010Publication date: January 13, 2011Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Takashi Ohsumi
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Patent number: 7667315Abstract: A semiconductor chip includes a semiconductor substrate having an opening portion and a frame portion defining a periphery of the opening portion. At least one electric element is provided on the frame portion, and has at least one electrode terminal. A first insulation film is formed on the frame portion so that the electrode terminal is partially exposed at the first insulation film to form a plurality of electrode pads.Type: GrantFiled: March 1, 2006Date of Patent: February 23, 2010Assignee: Oki Semiconductor Co., Ltd.Inventor: Takashi Ohsumi
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Patent number: 7528005Abstract: A method of manufacturing a semiconductor device includes providing a first semiconductor chip having a plurality of pads, providing a second semiconductor chip having a plurality of pads, fixing the second semiconductor chip over a main surface of the first semiconductor chip, forming an insulating layer between the first semiconductor chip and the second semiconductor chip, forming a plurality of conductive posts over the main surface of the first semiconductor chip and a main surface of the second semiconductor chip, electrically connecting the plurality of conductive posts to the plurality of pads on the first semiconductor chip and the plurality of pads on the second semiconductor chip and covering the main surfaces of the first and second semiconductor chips with a resin, the resin partially covering the plurality of conductive posts.Type: GrantFiled: June 1, 2004Date of Patent: May 5, 2009Assignee: Oki Semiconductor Co., Ltd.Inventors: Yoshikazu Takahashi, Takashi Ohsumi
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Publication number: 20090053856Abstract: A semiconductor device includes a substrate for transmitting light, a wiring layer provided on the substrate, a semiconductor chip formed on the wiring layer, a columnar electrode, a sealant, and an external connection terminal electrically connected to the semiconductor chip via the wiring layer and protruding electrode. The device includes a cut surface formed by dicing and constituted by only the substrate and the sealant. Since the cut surface has a single-layer structure as a result of forming the sealant in a single step, moisture cannot infiltrate through the sealant, hence a device resistant to corrosion and operational defects is provided.Type: ApplicationFiled: October 30, 2008Publication date: February 26, 2009Inventor: Takashi Ohsumi
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Patent number: 7358608Abstract: The present invention provides a semiconductor device wherein a passivation film, an insulating film and an encapsulating layer are formed, in this order, on the surface of a semiconductor substrate, which is provided with a electrode pad thereon, and a leading end portion of a bump electrode supported by the insulating film and electrically connected to the electrode pad is exposed from the surface of the encapsulating layer. In the semiconductor device, a slit-shaped opening, which extends along a peripheral edge of the bottom of the bump electrode, is defined in the insulating film.Type: GrantFiled: June 14, 2004Date of Patent: April 15, 2008Assignee: Oki Electric Industry Co., Ltd.Inventor: Takashi Ohsumi
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Patent number: 7180185Abstract: A semiconductor device includes a passivity film, an insulating film and an encapsulating layer, all of which are formed, in this order, on the surface of a semiconductor substrate provided with a connecting pad, and a bump electrode electrically connected to the connecting pad via a wiring passing through a first opening defined in the passivation film and a second opening defined in the insulating film. The bump electrode has a leading end portion exposed from the surface of the encapsulating layer.Type: GrantFiled: June 14, 2004Date of Patent: February 20, 2007Assignee: Oki Electric Industry Co., LtdInventor: Takashi Ohsumi
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Publication number: 20060267155Abstract: A semiconductor wafer has a substrate, and a plurality of active areas formed on the substrate. Integrated circuits are formed in the active areas. The semiconductor wafer also has dicing areas formed between the adjacent active areas. A seal ring is formed along the edge (periphery) of each active area. The semiconductor water also has interconnects formed closely to the inside of the seal ring. A protective layer covers the active areas. A protective film is formed on the protective layer at the locations of the active areas. The semiconductor wafer also has another interconnects formed on the protective film for electrical connection to the integrated circuits. Preferably, when the aspect ratio of a groove formed in the protective layer between the seal ring and the interconnect is 0.5 or more, this groove is covered with the protective film.Type: ApplicationFiled: May 26, 2006Publication date: November 30, 2006Inventor: Takashi Ohsumi
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Patent number: 7129579Abstract: A semiconductor apparatus includes a semiconductor integrated circuit including a conductive pattern; an insulating layer which is formed on the semiconductor integrated circuit to forms a plurality of base members having uneven heights; an opening which is formed through the insulating layer to expose a part of the conductive pattern; and a conductive layer which is formed on the insulating layer and the opening, the conductive layer is extending from the exposed portion of the conductive pattern to the top surface of the highest base member. An electrode is composed of the insulating layer, the opening and the conductive layer.Type: GrantFiled: March 17, 2003Date of Patent: October 31, 2006Assignee: Oki Electric Industry Co., Ltd.Inventor: Takashi Ohsumi
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Publication number: 20060214288Abstract: A semiconductor chip includes a semiconductor substrate having an opening portion and a frame portion defining a periphery of the opening portion. At least one electric element is provided on the frame portion, and has at least one electrode terminal. A first insulation film is formed on the frame portion so that the electrode terminal is partially exposed at the first insulation film to form a plurality of electrode pads.Type: ApplicationFiled: March 1, 2006Publication date: September 28, 2006Inventor: Takashi Ohsumi
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Patent number: 7045908Abstract: A semiconductor device which is manufactured through a process of forming a second structure on a first structure, by using a photolithography technique, the semiconductor device includes a mark which is provided at a part of the first structure to be covered by the second structure and which is necessary for forming the second structure.Type: GrantFiled: December 30, 2003Date of Patent: May 16, 2006Assignee: Oki Electric Industry Co., Ltd.Inventor: Takashi Ohsumi
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Publication number: 20060065964Abstract: A semiconductor device includes a substrate for transmitting light, a wiring layer provided on the substrate, a semiconductor chip formed on the wiring layer, a columnar electrode, a sealant, and an external connection terminal electrically connected to the semiconductor chip via the wiring layer and protruding electrode. The device includes a cut surface formed by dicing and constituted by only the substrate and the sealant. Since the cut surface has a single-layer structure as a result of forming the sealant in a single step, moisture cannot infiltrate through the sealant, hence a device resistant to corrosion and operational defects is provided.Type: ApplicationFiled: September 20, 2005Publication date: March 30, 2006Inventor: Takashi Ohsumi
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Patent number: 6979592Abstract: A semiconductor apparatus having a semiconductor substrate including an integrated circuit and an insulative base member formed on a main surface thereof. A conductive layer is formed on the main surface of the semiconductor substrate as coupled to the integrated circuit and includes an external portion that extends onto top surface of the base member. A sealing member is formed on the main surface of the semiconductor substrate, the conductive layer and side surfaces of the base member, whereby the extended portion of the conductive layer is exposed from the sealing member.Type: GrantFiled: October 22, 2003Date of Patent: December 27, 2005Assignee: Oki Electric Industry Co., Ltd.Inventor: Takashi Ohsumi
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Patent number: 6893943Abstract: A method for dividing a semiconductor wafer which is covered by an opaque resin in a dicing process includes forming marks on the semiconductor wafer, wherein the marks are distinguished from electrodes which are formed on the semiconductor wafer. According to the method, in a dicing process, separating semiconductor chips from the semiconductor wafer can be precisely achieved.Type: GrantFiled: May 8, 2003Date of Patent: May 17, 2005Assignee: Oki Electric Industry Co., Ltd.Inventors: Takashi Ohsumi, Yuzo Kato
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Publication number: 20050059200Abstract: A semiconductor apparatus includes a semiconductor integrated circuit including a conductive pattern; an insulating layer which is formed on the semiconductor integrated circuit to forms a plurality of base members having uneven heights; an opening which is formed through the insulating layer to expose a part of the conductive pattern; and a conductive layer which is formed on the insulating layer and the opening, the conductive layer is extending from the exposed portion of the conductive pattern to the top surface of the highest base member. An electrode is composed of the insulating layer, the opening and the conductive layer.Type: ApplicationFiled: October 5, 2004Publication date: March 17, 2005Inventor: Takashi Ohsumi
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Patent number: 6852617Abstract: In one embodiment of the invention, a plurality of posts (terminals) stands on a main surface of a semiconductor substrate. A first metal electrode is formed on a side face of each post before providing a sealing layer over the main surface of the semiconductor substrate. The first metal electrode constitutes a portion of an external terminal. After providing the sealing layer, a second metal electrode is formed on each post and the associated first metal electrode. Then, an “alloy” of the first and second metal electrodes is formed by heating these electrodes. Accordingly, the external terminal can be formed on the top face and side face of each post without carrying out a step of removing the sealing layer by means of a laser.Type: GrantFiled: February 5, 2004Date of Patent: February 8, 2005Assignee: Oki Electric Industry Co., Ltd.Inventors: Yoshinori Shizuno, Takashi Ohsumi
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Publication number: 20050017356Abstract: A semiconductor device includes a passivation film, an insulating film and an encapsulating layer, all of which are formed, in this order, on the surface of a semiconductor substrate provided with a connecting pad, and a bump electrode electrically connected to the connecting pad via a wiring passing through a first opening defined in the passivation film and a second opening defined in the insulating film. The bump electrode has a leading end portion exposed from the surface of the encapsulating layer.Type: ApplicationFiled: June 14, 2004Publication date: January 27, 2005Inventor: Takashi Ohsumi
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Publication number: 20050012210Abstract: The present invention provides a semiconductor device wherein a passivation film, an insulating film and an encapsulating layer are formed, in this order, on the surface of a semiconductor substrate, which is provided with a electrode pad thereon, and a leading end portion of a bump electrode supported by the insulating film and electrically connected to the electrode pad is exposed from the surface of the encapsulating layer. In the semiconductor device, a slit-shaped opening, which extends along a peripheral edge of the bottom of the bump electrode, is defined in the insulating film.Type: ApplicationFiled: June 14, 2004Publication date: January 20, 2005Inventor: Takashi Ohsumi