Patents by Inventor Takashi Okuda
Takashi Okuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11135102Abstract: A plurality of openings (11) is formed in a region corresponding to at least a body fluid discharge region (H) of a liquid permeable top sheet (3). A polymer sheet (6) disposed adjacent to a surface of an absorbent body (4) side of the liquid permeable top sheet (3) is included, and the polymer sheet includes highly absorbent resin disposed along a longitudinal direction on both sides of the region corresponding to the body fluid discharge region (H). Upon the highly absorbent resin becoming swollen by absorption, a space (10) for holding a body fluid is formed between regions in which the highly absorbent resin is disposed (12) and also between the liquid permeable top sheet (3) and the polymer sheet (6).Type: GrantFiled: February 24, 2017Date of Patent: October 5, 2021Assignee: DAIO PAPER CORPORATIONInventor: Takashi Okuda
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Publication number: 20190083329Abstract: A plurality of openings (11) is formed in a region corresponding to at least a body fluid discharge region (H) of a liquid permeable top sheet (3). A polymer sheet (6) disposed adjacent to a surface of an absorbent body (4) side of the liquid permeable top sheet (3) is included, and the polymer sheet includes highly absorbent resin disposed along a longitudinal direction on both sides of the region corresponding to the body fluid discharge region (H). Upon the highly absorbent resin becoming swollen by absorption, a space (10) for holding a body fluid is formed between regions in which the highly absorbent resin is disposed (12) and also between the liquid permeable top sheet (3) and the polymer sheet (6).Type: ApplicationFiled: February 24, 2017Publication date: March 21, 2019Inventor: Takashi OKUDA
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Patent number: 10170486Abstract: Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.Type: GrantFiled: March 29, 2016Date of Patent: January 1, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tomoaki Atsumi, Takashi Okuda
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Patent number: 9921983Abstract: Two channels of a main CPU channel and a sub CPU channel each including a reception channel and a transmission channel, and performing a data transfer by a DMA in accordance with a descriptor are provided, a channel switching part selects the main CPU channel or the sub CPU channel in accordance with information set at a mode setting register, and performs a switching of channels at a boundary of a packet to be transferred to thereby enable the switching of channels without interrupting a DMA operation.Type: GrantFiled: August 27, 2014Date of Patent: March 20, 2018Assignee: SOCIONEXT INC.Inventors: Takashi Okuda, Satoru Okamoto
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Publication number: 20160211267Abstract: Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.Type: ApplicationFiled: March 29, 2016Publication date: July 21, 2016Inventors: Tomoaki ATSUMI, Takashi OKUDA
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Patent number: 9318374Abstract: Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.Type: GrantFiled: September 7, 2012Date of Patent: April 19, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tomoaki Atsumi, Takashi Okuda
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Patent number: 9118341Abstract: A delta-sigma A/D converter having plural input channels comprises a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.Type: GrantFiled: June 14, 2012Date of Patent: August 25, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Matsumoto, Toshio Kumamoto, Takashi Okuda
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Patent number: 9076505Abstract: A memory device including first to fourth memory cell arrays and a driver circuit including a pair of bit line driver circuits and a pair of word line driver circuits is provided. The first to fourth memory cell arrays are overlap with the driver circuit. Each of the pair of bit line driver circuits and a plurality of bit lines are connected through connection points on an edge along the boundary between the first and second memory cell arrays or on an edge along the boundary between the third and fourth memory cell arrays. Each of the pair of word line driver circuits and a plurality of word lines are connected through second connection points on an edge along the boundary between the first and fourth memory cell arrays or on an edge along the boundary between the second and third memory cell arrays.Type: GrantFiled: December 5, 2012Date of Patent: July 7, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tomoaki Atsumi, Takashi Okuda
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Patent number: 9065471Abstract: A delta-sigma modulator is configured to feedback an output signal of a quantizer to an input of an integrator, and also feedback to the input of the integrator a differentiated error signal representing derivative of quantization error caused by the quantizer.Type: GrantFiled: November 20, 2014Date of Patent: June 23, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Takashi Okuda
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Publication number: 20150171887Abstract: A delta-sigma modulator is configured to feedback an output signal of a quantizer to an input of an integrator, and also feedback to the input of the integrator a differentiated error signal representing derivative of quantization error caused by the quantizer.Type: ApplicationFiled: November 20, 2014Publication date: June 18, 2015Inventor: Takashi OKUDA
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Publication number: 20150120983Abstract: Two channels of a main CPU channel and a sub CPU channel each including a reception channel and a transmission channel, and performing a data transfer by a DMA in accordance with a descriptor are provided, a channel switching part selects the main CPU channel or the sub CPU channel in accordance with information set at a mode setting register, and performs a switching of channels at a boundary of a packet to be transferred to thereby enable the switching of channels without interrupting a DMA operation.Type: ApplicationFiled: August 27, 2014Publication date: April 30, 2015Inventors: Takashi OKUDA, Satoru OKAMOTO
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Patent number: 8942029Abstract: A memory device including first to fourth memory cell arrays and a driver circuit including a pair of bit line driver circuits and a pair of word line driver circuits is provided. The first to fourth memory cell arrays are overlap with the driver circuit. Each of the pair of bit line driver circuits and a plurality of bit lines are connected through connection points on an edge along the boundary between the first and second memory cell arrays or on an edge along the boundary between the third and fourth memory cell arrays. Each of the pair of word line driver circuits and a plurality of word lines are connected through second connection points on an edge along the boundary between the first and fourth memory cell arrays or on an edge along the boundary between the second and third memory cell arrays.Type: GrantFiled: December 5, 2012Date of Patent: January 27, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tomoaki Atsumi, Takashi Okuda
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Publication number: 20130069132Abstract: Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.Type: ApplicationFiled: September 7, 2012Publication date: March 21, 2013Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Tomoaki Atsumi, Takashi Okuda
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Publication number: 20130057419Abstract: A delta-sigma A/D converter having plural input channels comprises a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.Type: ApplicationFiled: June 14, 2012Publication date: March 7, 2013Applicant: Renesas Electronics CorporationInventors: Takashi MATSUMOTO, Toshio KUMAMOTO, Takashi OKUDA
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Patent number: 8330199Abstract: To eliminate the substrate voltage dependences of the respective resistance values of resistor elements, in the resistor elements coupled in series to each other over respective substrate regions, the ends of the resistor elements are coupled to the corresponding substrate regions by respective bias wires such that respective average potentials between the substrate regions of the resistor elements and the corresponding resistor elements have opposite polarities, and equal magnitudes.Type: GrantFiled: September 30, 2009Date of Patent: December 11, 2012Assignee: Renesas Electronics CorporationInventors: Masaomi Kamakura, Toshio Kumamoto, Takashi Okuda
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Patent number: 8237282Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.Type: GrantFiled: February 18, 2011Date of Patent: August 7, 2012Assignees: Renesas Electronics Corporation, Renesas Device Design Corp.Inventors: Takashi Okuda, Yasuo Morimoto, Yuko Maruyama, Toshio Kumamoto
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Patent number: 8223050Abstract: In a delta-sigma A/D converter provided with plural channels for converting an analog input signal into a digital signal, an adverse influence of an idle tone is reduced in each channel. The delta-sigma A/D converter comprises: a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.Type: GrantFiled: October 25, 2010Date of Patent: July 17, 2012Assignee: Renesas Electronics CorporationInventors: Takashi Matsumoto, Toshio Kumamoto, Takashi Okuda
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Patent number: 8188526Abstract: It is an object of the present invention to surely protect a predetermined semiconductor element or a predetermined semiconductor element group in an analog block from a noise generated from a digital block. A semiconductor device according to the present invention includes a semiconductor substrate, a digital block to be a region in which a digital circuit is formed and an analog block to be a region in which an analog circuit is formed, arranged by separating an upper surface of the semiconductor substrate and a substrate potential fixing region provided on the semiconductor substrate so as to surround in a planar view the predetermined semiconductor element group in the analog block, and a pad connected to the substrate potential fixing region and receiving a predetermined potential from an external part.Type: GrantFiled: December 2, 2010Date of Patent: May 29, 2012Assignee: Renesas Electronics CorporationInventors: Takashi Okuda, Toshio Kumamoto
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Patent number: 8173790Abstract: An objective of the present invention is to provide polynucleotides encoding insect desiccation resistance proteins, and uses thereof cDNA libraries were produced from Polypedilum vanderplanki larvae in a desiccated state, a P. vanderplanki EST database was constructed, and genes encoding LEA proteins were isolated. This resulted in the successful isolation of three types of novel gene encoding LEA-like proteins (PvLEA1, PvLEA2, and PvLEA3.) When secondary structure predictions and motif searches were performed on the proteins deduced from each of the genes, all three proteins had ?-helix-rich structures and LEA_4 motifs, which are characteristic of LEA proteins. Moreover, the recombinant proteins synthesized from PvLEA1, 2 and 3 genes were heat soluble even when boiling, so that PvLEA1, 2 and 3 proteins have highly hydrophilic property as well as plant LEA proteins. Therefore, the three isolated genes were found to be novel P. vanderplanki-derived LEA genes.Type: GrantFiled: May 9, 2011Date of Patent: May 8, 2012Assignee: National Institute of Agrobiological SciencesInventors: Takahiro Kikawada, Takashi Okuda, Masahiko Watanabe, Kazuei Mita, Keiko Kadono
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Patent number: 8098988Abstract: A disclosed optical add/drop multiplexing device demultiplexes a first signal into multiple signals according to wavelengths, drops one or more of the demultiplexed signals to a transponder, adds one or more signals output from the transponder, multiplexes these signals into a second signal, and outputs it. The device includes an injecting unit for injecting one of measurement signals, each of whose wavelength corresponds to that of a different demultiplexed signal, into a core of a multicore cable within the device, the core being used to transmit the different demultiplexed signal having the corresponding wavelength; a preventing unit for preventing the one measurement signal from emanating; a measuring unit for measuring, for each wavelength, levels of the one measurement signal before and after the corresponding core; a calculating unit for calculating loss of the corresponding core, based on the measured levels; and an informing unit for reporting the calculated loss.Type: GrantFiled: December 24, 2008Date of Patent: January 17, 2012Assignee: Fujitsu LimitedInventors: Hiroaki Nakazato, Hiroyuki Hanazawa, Takashi Okuda