Patents by Inventor Takashi Onizawa
Takashi Onizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190296138Abstract: A semiconductor apparatus according to the present embodiment is a semiconductor apparatus including a first nitride semiconductor layer including a first region having a first upper surface, a second region having a second upper surface parallel to the first upper surface, and a third region provided between the first region and the second region and having a third upper surface inclined with respect to the first upper surface and the second upper surface; a second nitride semiconductor layer including a fourth upper surface provided above the first upper surface, a fifth upper surface provided above the second upper surface, and a sixth upper surface provided above the third upper surface and being parallel to the third upper surface, the fourth upper surface being parallel to the first upper surface and being a +c face, the fifth upper surface parallel to the second upper surface and being a +c face, and the second nitride semiconductor having a bandgap larger than that of the first nitride semiconductor lType: ApplicationFiled: August 31, 2018Publication date: September 26, 2019Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Hiroaki HAYASHI, Seiji INUMIYA, Takashi ONIZAWA, Emiko INOUE
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Patent number: 9722067Abstract: A semiconductor device includes a first nitride semiconductor layer, a source electrode on the first nitride semiconductor layer, a drain electrode on the first nitride semiconductor layer, a gate electrode on the first nitride semiconductor layer and between the source electrode and the drain electrode, a gate field plate electrode that is separated from the first nitride semiconductor layer, and includes one end in direct contact with the gate electrode, and the other end positioned between the gate electrode and the drain electrode, a first interlayer insulating film that is separated from the gate electrode and is between the gate field plate electrode and the first nitride semiconductor layer, and a second interlayer insulating film that is between the gate electrode and the first interlayer insulating film and has a dielectric constant higher than a dielectric constant of the first interlayer insulating film.Type: GrantFiled: March 7, 2016Date of Patent: August 1, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tasuku Ono, Takashi Onizawa, Yoshikazu Suzuki
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Publication number: 20170077284Abstract: A semiconductor device includes a first nitride semiconductor layer, a source electrode on the first nitride semiconductor layer, a drain electrode on the first nitride semiconductor layer, a gate electrode on the first nitride semiconductor layer and between the source electrode and the drain electrode, a gate field plate electrode that is separated from the first nitride semiconductor layer, and includes one end in direct contact with the gate electrode, and the other end positioned between the gate electrode and the drain electrode, a first interlayer insulating film that is separated from the gate electrode and is between the gate field plate electrode and the first nitride semiconductor layer, and a second interlayer insulating film that is between the gate electrode and the first interlayer insulating film and has a dielectric constant higher than a dielectric constant of the first interlayer insulating film.Type: ApplicationFiled: March 7, 2016Publication date: March 16, 2017Inventors: Tasuku ONO, Takashi ONIZAWA, Yoshikazu SUZUKI
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Publication number: 20170077279Abstract: A semiconductor device includes a semiconductor substrate which includes a first surface, a second surface, and an end portion, the semiconductor substrate including a first region of a p-type and a second region of an n-type provided in a corner portion of the semiconductor substrate between the first surface and the end surface, a nitride semiconductor layer on the first surface, and an electrode on the nitride semiconductor layer.Type: ApplicationFiled: March 4, 2016Publication date: March 16, 2017Inventor: Takashi ONIZAWA
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Publication number: 20160268410Abstract: A semiconductor device includes: a substrate; a first compound semiconductor layer provided on the substrate; a second compound semiconductor layer provided on the first compound semiconductor layer and having a band gap larger than that of the first compound semiconductor layer; a first element isolation region provided in the first compound semiconductor layer and the second compound semiconductor layer; and a first electrode and a second electrode which are electrically connected to a first conductive region formed from the first and second compound semiconductor layers arranged outside the first element isolation region.Type: ApplicationFiled: September 1, 2015Publication date: September 15, 2016Inventors: Takashi Onizawa, Yoshiharu Takada
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Publication number: 20160218067Abstract: A semiconductor device includes a substrate, a nitride semiconductor layer formed on the substrate, and a protection layer, comprising carbon, covering a side surface of the nitride semiconductor layer.Type: ApplicationFiled: August 31, 2015Publication date: July 28, 2016Inventors: Shingo MASUKO, Yoshiharu TAKADA, Takashi ONIZAWA, Yasuhiro ISOBE, Kohei OASA
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Patent number: 9362110Abstract: A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four ? atoms and hexa-coordinated Al atoms each surrounded by six ? atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms.Type: GrantFiled: August 23, 2014Date of Patent: June 7, 2016Assignee: Renesas Electronics CorporationInventors: Nobuyuki Ikarashi, Takashi Onizawa, Motofumi Saitoh
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Patent number: 9330905Abstract: A semiconductor device, in which the generation of interface states in the interface region between a nitride semiconductor layer and an aluminum oxide layer is suppressed, includes a first nitride semiconductor layer and an aluminum oxide layer. The first nitride semiconductor layer includes Ga. The aluminum oxide layer directly contacts the upper surface of the first nitride semiconductor layer, and includes H (hydrogen) atoms at least within a defined region from the interface with the first nitride semiconductor layer. In addition, the peak value of an H atom concentration in the above region is in a range of 1×1020 cm?3 to 5×1021 cm?3.Type: GrantFiled: March 18, 2013Date of Patent: May 3, 2016Assignee: Renesas Electronics CorporationInventor: Takashi Onizawa
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Publication number: 20160086939Abstract: A first contact, a second impurity region, and a second low-concentration impurity region form a Schottky barrier diode. The second impurity region has the same impurity concentration as those of first impurity regions, and thus can be formed in the same process as forming the first impurity regions. In addition, the second low-concentration impurity region has the same impurity concentration as those of first low-concentration impurity regions, and thus can be formed in the same process as forming the first low-concentration impurity regions.Type: ApplicationFiled: September 23, 2015Publication date: March 24, 2016Inventors: Hiroshi Takeda, Kiyoshi Takeuchi, Takashi Onizawa, Masayasu Tanaka
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Publication number: 20160049375Abstract: A semiconductor device includes a substrate which includes a first face. The device also includes a buffer layer, a semiconductor layer, source and drain electrodes, and a gate electrode. A trench is formed on the semiconductor layer so that the trench surrounds the source electrode, the drain electrode, and the gate electrode in a plan view, the trench passes through the semiconductor layer and the buffer layer, and a bottom of the trench reaches at least an inside of the substrate. A distance from the first face of the substrate to the bottom of the trench is 100 nm or more in a thickness direction of the substrate.Type: ApplicationFiled: October 28, 2015Publication date: February 18, 2016Inventors: Ippei KUME, Takashi ONIZAWA, Takashi HASE, Shigeru HIRAO, Tadatoshi DANNO
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Patent number: 9196731Abstract: Sometimes to warp a group III nitride semiconductor and a silicon by the stress of the group III nitride semiconductor acting on the silicon. A semiconductor device includes a substrate, a buffer layer, and a semiconductor layer. A trench is formed on a sixth face of the semiconductor layer. The trench passes through the semiconductor layer and the buffer layer. The bottom of the trench reaches at least the inside of the substrate.Type: GrantFiled: August 8, 2014Date of Patent: November 24, 2015Assignee: Renesas Electronics CorporationInventors: Ippei Kume, Takashi Onizawa, Takashi Hase, Shigeru Hirao, Tadatoshi Danno
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Patent number: 9178059Abstract: A first contact, a second impurity region, and a second low-concentration impurity region form a Schottky barrier diode. The second impurity region has the same impurity concentration as those of first impurity regions, and thus can be formed in the same process as forming the first impurity regions. In addition, the second low-concentration impurity region has the same impurity concentration as those of first low-concentration impurity regions, and thus can be formed in the same process as forming the first low-concentration impurity regions.Type: GrantFiled: September 26, 2013Date of Patent: November 3, 2015Assignee: Renesas Electronics CorporationInventors: Hiroshi Takeda, Kiyoshi Takeuchi, Takashi Onizawa, Masayasu Tanaka
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Publication number: 20150060942Abstract: Sometimes to warp a group III nitride semiconductor and a silicon by the stress of the group III nitride semiconductor acting on the silicon. A semiconductor device includes a substrate, a buffer layer, and a semiconductor layer. A trench is formed on a sixth face of the semiconductor layer. The trench passes through the semiconductor layer and the buffer layer. The bottom of the trench reaches at least the inside of the substrate.Type: ApplicationFiled: August 8, 2014Publication date: March 5, 2015Inventors: Ippei Kume, Takashi Onizawa, Takashi Hase, Shigeru Hirao, Tadatoshi Danno
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Publication number: 20140363982Abstract: A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four ? atoms and hexa-coordinated Al atoms each surrounded by six ? atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms.Type: ApplicationFiled: August 23, 2014Publication date: December 11, 2014Inventors: Nobuyuki Ikarashi, Takashi Onizawa, Motofumi Saitoh
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Patent number: 8872234Abstract: A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four O atoms and hexa-coordinated Al atoms each surrounded by six O atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms.Type: GrantFiled: January 4, 2013Date of Patent: October 28, 2014Assignee: Renesas Electronics CorporationInventors: Nobuyuki Ikarashi, Takashi Onizawa, Motofumi Saitoh
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Publication number: 20140084386Abstract: A first contact, a second impurity region, and a second low-concentration impurity region form a Schottky barrier diode. The second impurity region has the same impurity concentration as those of first impurity regions, and thus can be formed in the same process as forming the first impurity regions. In addition, the second low-concentration impurity region has the same impurity concentration as those of first low-concentration impurity regions, and thus can be formed in the same process as forming the first low-concentration impurity regions.Type: ApplicationFiled: September 26, 2013Publication date: March 27, 2014Applicant: Renesas Electronics CorporationInventors: Hiroshi Takeda, Kiyoshi Takeuchi, Takashi Onizawa, Masayasu Tanaka
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Publication number: 20130264576Abstract: A semiconductor device, in which the generation of interface states in the interface region between a nitride semiconductor layer and an aluminum oxide layer is suppressed, includes a first nitride semiconductor layer and an aluminum oxide layer. The first nitride semiconductor layer includes Ga. The aluminum oxide layer directly contacts the upper surface of the first nitride semiconductor layer, and includes H (hydrogen) atoms at least within a defined region from the interface with the first nitride semiconductor layer. In addition, the peak value of an H atom concentration in the above region is in a range of 1×1020 cm?3 to 5×1021 cm?3.Type: ApplicationFiled: March 18, 2013Publication date: October 10, 2013Applicant: Renesas Electronics CorporationInventor: Takashi Onizawa
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Patent number: 8551842Abstract: A method of manufacturing a semiconductor device includes performing heat treatment for activating impurities of a transistor having a gate electrode over a gate insulating film with a higher relative permittivity than a silicon oxynitride film or a silicon oxide film. In the heat treatment, a first heat treatment, in which a wafer surface is heated at a temperature of 800 to 1000° C. in 5 to 50 milliseconds by low-output flash lamp annealing or laser annealing, and a second heat treatment, in which the wafer surface is heated at a temperature equal to or more than of 1100° C. in 0.1 to 10 milliseconds by flash lamp annealing or laser annealing with a higher output than in the first heat treatment, are performed in this order.Type: GrantFiled: May 27, 2010Date of Patent: October 8, 2013Assignee: Renesas Electronics CorporationInventor: Takashi Onizawa
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Publication number: 20100317200Abstract: A method of manufacturing a semiconductor device includes performing heat treatment for activating impurities of a transistor having a gate electrode over a gate insulating film with a higher relative permittivity than a silicon oxynitride film or a silicon oxide film. In the heat treatment, a first heat treatment, in which a wafer surface is heated at a temperature of 800 to 1000° C. in 5 to 50 milliseconds by low-output flash lamp annealing or laser annealing, and a second heat treatment, in which the wafer surface is heated at a temperature equal to or more than of 1100° C. in 0.1 to 10 milliseconds by flash lamp annealing or laser annealing with a higher output than in the first heat treatment, are performed in this order.Type: ApplicationFiled: May 27, 2010Publication date: December 16, 2010Applicant: NEC Electronics CorporationInventor: Takashi Onizawa
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Publication number: 20090311840Abstract: A method of manufacturing a semiconductor device includes forming, over a substrate, a gate insulating film containing a high-k insulating film which is composed of a material having a dielectric constant larger than that of silicon dioxide film; forming a gate electrode containing a metal over the gate insulating film; forming extension regions by implanting an dopant into the substrate using the gate electrode as a mask; and annealing the substrate, having the dopant implanted therein, by flash lamp annealing or laser annealing; wherein the annealing further includes: a first step irradiating a substrate with a light pulse having a predetermined peak intensity; and a second step irradiating a substrate with light pulses having peak intensities lower than that of the light pulse used in the first step.Type: ApplicationFiled: June 15, 2009Publication date: December 17, 2009Applicant: NEC ELECTRONICS CORPORATIONInventor: Takashi ONIZAWA