Patents by Inventor Takashi Shigematsu

Takashi Shigematsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6697399
    Abstract: A bottom plate (4a) of a box-shaped package (4) is made of a metal. Portions of the package (4) (peripheral wall (4b) and cover plate (4c)) other than the bottom plate (4a) are made of a resin or a ceramic that is more economical than the metal. The material cost of the package (4) can thus be reduced in comparison with the case where the package (4) is made of the metal as a whole. A Peltier module (5) is fixed to the bottom plate (4a). A base (6) is fixed over the Peltier module (5), and a semiconductor laser chip (2) is disposed on this base (6). Heat from the semiconductor laser chip (2) and from the Peltier module (5) can be efficiently radiated through the bottom plate (4a) made of the metal, and deterioration of heat radiation performance can be prevented.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: February 24, 2004
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Toshio Kimura, Takashi Shigematsu, Shinichiro Iizuka, Takeshi Aikiyo
  • Publication number: 20030179993
    Abstract: An optical module includes first and second fiber units that hold end portions of first and second optical fibers, and first and second collimators disposed between these fiber units and having first and second lenses, respectively. End faces of the first and second optical fibers are disposed on imaginary circumferences on the end faces of the first and second fiber units. Laser light beams from the end face of the first optical fiber are collimated by the first lens and then focused by the second lens, and enter the end face of the second optical fiber that is disposed diametrically opposite to the first optical fiber with respect to the center axis of the optical module.
    Type: Application
    Filed: January 6, 2003
    Publication date: September 25, 2003
    Applicant: The Furukawa Electric Co., Ltd.
    Inventors: Takashi Shigenaga, Katsuki Suematsu, Hiroshi Matsuura, Renichi Yuguchi, Takashi Shigematsu
  • Publication number: 20030124806
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: December 23, 2002
    Publication date: July 3, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 6512265
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: January 28, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20030016909
    Abstract: An optical module comprises an optical fiber having a formed portion to form a fiber grating and a package to which the optical fiber is secured. The package comprises a single package member or at least two or more package members whose materials differ from each other. The optical fiber is secured to the package member. A distortion for adjusting a Bragg reflection wavelength of the fiber grating of the optical fiber is given to the package member.
    Type: Application
    Filed: May 14, 2002
    Publication date: January 23, 2003
    Inventors: Atsushi Shinozaki, Takashi Shigematsu, Toshihiko Ota, Shigehito Yodo
  • Publication number: 20030016910
    Abstract: An optical module comprising: a comb-shaped package having a plurality of teeth portions and a base portion; and at least one optical fiber having fiber grating, wherein respective fiber-grating formed portions of at least one optical fiber are placed in corresponding teeth portions and base portion of said package, and the optical fiber is fixed to the base portion and corresponding teeth portion in such manner that the fiber-grating formed portion exists between the base portion and the corresponding teeth portion.
    Type: Application
    Filed: May 29, 2002
    Publication date: January 23, 2003
    Inventors: Atsushi Shinozaki, Takashi Shigematsu, Toshihiko Ota, Shigehito Yodo
  • Publication number: 20030001297
    Abstract: A method for manufacturing an optical connector ferrule according to the present invention is a method for manufacturing an optical connector ferrule where a plurality of fiber holes are arranged between two guide pin holes, wherein melted material resin is injected from one resin injection port into a cavity of a forming mold where two forming pins for forming the guide pin holes and a plurality of forming pins for forming the fiber hole are arranged in parallel to one another. A forming mold according to the present invention is provided with a cavity where a plurality of forming pins can be arranged in parallel to one another, and one resin injection port through which melted material resin can be injected into the cavity.
    Type: Application
    Filed: October 19, 2001
    Publication date: January 2, 2003
    Inventors: Katsuki Suematsu, Yasushi Kihara, Takashi Shigematsu
  • Publication number: 20020146480
    Abstract: A manufacturing apparatus for multi-fiber optical ferrule includes a spacer whose hardness is equivalent to or higher than the hardness of pins for forming fiber holes. Further, corner portions with respect to the arrangement direction of the pins for forming fiber holes of the spacer are formed as inclined surfaces or rounded surfaces.
    Type: Application
    Filed: January 22, 2002
    Publication date: October 10, 2002
    Inventors: Jun Yamakawa, Masahiro Hirao, Yasushi Kihara, Takashi Shigematsu
  • Publication number: 20020098656
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: March 27, 2002
    Publication date: July 25, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 6410959
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: June 25, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20020009867
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: September 21, 2001
    Publication date: January 24, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20020003819
    Abstract: A bottom plate (4a) of a box-shaped package (4) is made of a metal. Portions of the package (4) (peripheral wall (4b) and cover plate (4c)) other than the bottom plate (4a) are made of a resin or a ceramic that is more economical than the metal. The material cost of the package (4) can thus be reduced in comparison with the case where the package (4) is made of the metal as a whole. A Peltier module (5) is fixed to the bottom plate (4a). A base (6) is fixed over the Peltier module (5), and a semiconductor laser chip (2) is disposed on this base (6). Heat from the semiconductor laser chip (2) and from the Peltier module (5) can be efficiently radiated through the bottom plate (4a) made of the metal, and deterioration of heat radiation performance can be prevented.
    Type: Application
    Filed: May 25, 2001
    Publication date: January 10, 2002
    Applicant: THE FURUKAWA ELECTRIC CO., LTD.
    Inventors: Toshio Kimura, Takashi Shigematsu, Shinichiro Iizuka, Takeshi Aikiyo
  • Patent number: 6307231
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: October 23, 2001
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 6270263
    Abstract: An optical module comprises a substrate (2), formed with wiring patterns for electrical signals and having a mounting surface (2b) mounted with one or more semiconductor optical elements (4), and a package (7, 8) in which the substrate (2) is located. The substrate (2) is formed with at least one first positioning section (2c), the package (7) is formed of a synthetic resin and includes a disposition section (7e) in which one or more optical waveguide components are opposed to the semiconductor optical elements (4), and a second positioning section (7g) adapted to engage the first positioning section, thereby positioning the semiconductor optical elements and the disposition section.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: August 7, 2001
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Masayuki Iwase, Hajime Mori, Takashi Shigematsu
  • Patent number: 6168996
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: August 20, 1998
    Date of Patent: January 2, 2001
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 5707565
    Abstract: A method for manufacturing a ferrule having butt end face on the front and positioning holes on both sides in the width direction and formed with plurality of fiber holes for inserting optical fibers, arranged in such a manner as to be inclined in the thickness direction, by using at least two molds which are arranged in an opposed manner and either or both of which can be moved in the opening/closing direction. Each of at least two molds has a first forming wall for forming the butt end face and a second forming wall for forming a working portion for applying a pressing force perpendicular to the butt end face at the rear of the ferrule. A core for forming the fiber hole and molding pins for forming the positioning holes are arranged in parallel and held in such a manner as to be inclined at a predetermined angle .theta. in the thickness direction of the ferrule molded by at least two molds.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: January 13, 1998
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Kenji Suzuki, Hiroyuki Yamada, Koichi Takagi, Takashi Shigematsu, Mikio Ishihara
  • Patent number: 5706378
    Abstract: An optical waveguide chip assembly in which a plurality of optical waveguide patterns and two positioning grooves are laterally arranged is prepared by forming a plurality of optical waveguide patterns and two positioning grooves on a wafer in parallel to each other and cutting the wafer. Separately from this, an optical fiber array assembly having a plurality of optical fiber array cables and two guide pin holes is prepared. The optical waveguide chip assembly and the optical fiber array assembly are joined while aligning by the guide pins and then divided into units of individual optical waveguide modules. A large number of optical waveguide modules can be made with a good efficiency, and the mass productivity is improved. Since a plurality of optical waveguide modules are made by the same positioning, variations among products can be reduced.
    Type: Grant
    Filed: April 3, 1996
    Date of Patent: January 6, 1998
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Kenji Suzuki, Takashi Shigematsu
  • Patent number: 5631985
    Abstract: An optical connector including a ferrule having a butt end face at a front portion thereof and positioning holes formed at opposite sides of the ferrule in a widthwise direction of the ferrule. A plurality of optical fibers are coupled to the ferrule, and the optical connector is adapted to be abutted against another optical connector in an abutting direction. The positioning pin holes and the plurality of optical fibers are arranged in parallel with each other at least in the vicinity of the butt end face of the ferrule so that an arrangement plane of the plurality of optical fibers and the positioning pin holes is inclined at an inclination angle of .theta. with respect to a plane of the abutting direction, and so that a line where the butt end face and the arrangement plane cross each other is orthogonal to each axis of the plurality of optical fibers.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: May 20, 1997
    Assignees: The Furukawa Electric Co., Ltd., Nippon Telegraph and Telephone Corporation
    Inventors: Hiroyuki Yamada, Kenji Suzuki, Koichi Takagi, Takashi Shigematsu, Mikio Ishihara, Jun Yamakawa, Shinji Nagasawa
  • Patent number: 5629669
    Abstract: A driver regards a relative acceleration of a subject vehicle with respect to an object such as a preceding vehicle, an obstacle and the like as one having highest priority, and performs control such that deceleration is immediately started even if a relative velocity is small if the relative acceleration is large. Taking note of this point, the relative acceleration between the subject vehicle and the object is detected, and it is judged whether or not the subject vehicle and the object relatively approach each other at a relative acceleration not less than a predetermined value. A vehicle velocity is controlled such that the relative acceleration is not more than a predetermined target relative acceleration (for which a direction for approach is positive) when the subject vehicle and the object relatively approach each other at a relative acceleration not less than the predetermined value. Thus, the start of deceleration felt by the driver is adequate.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: May 13, 1997
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Katsuhiro Asano, Yoshikazu Hattori, Masashi Mizukoshi, Takashi Shigematsu
  • Patent number: 5548675
    Abstract: An optical fiber end portion (10) which has a ferrule (11) which comprises a butting end face (11e) opposed to or butted against an optical device (20), and a single fiber hole or a plurality of fiber holes formed in parallel at predetermined intervals, into which one end of optical fiber (13a) is inserted, the optical fiber being optically connected to said optical device, a method for manufacturing the optical fiber end portion, and a construction for connecting the end portion to the optical device. The ferrule is formed of a molded product of synthetic resin, and is provided with at least one connecting member (12) on the side of butting end face connected to the optical device. The connecting member (12) has a linear expansion coefficient set at a value smaller than the linear expansion coefficient of a synthetic resin forming the ferrule.
    Type: Grant
    Filed: November 8, 1994
    Date of Patent: August 20, 1996
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Takashi Shigematsu, Hisaharu Yanagawa, Takeo Shimizu, Shiro Nakamura, Kazuya Fukasawa, Tomohiro Watanabe