Abstract: A vehicle control apparatus executes a driving force limiting control when a mistaken operation condition is satisfied. The vehicle control apparatus determines that the mistaken operation condition is satisfied when a third condition is satisfied at a point in time when a second condition becomes satisfied, determines that the mistaken operation condition is not satisfied when the third condition is not satisfied at a point in time when the second condition becomes satisfied, the third condition becomes satisfied within a first time threshold since a first condition becomes satisfied, and a pressing condition is satisfied before the third condition becomes satisfied, and determines that the pressing condition is satisfied when an operation amount of an acceleration operator is greater than or equal to a positive second operation amount threshold, and an operation speed of the acceleration operator is greater than or equal to a positive second operation speed threshold.

Abstract: A backup power system according to the present disclosure includes a battery, a charging circuit, power storage, a first load, a second load, and a controller that controls the charging circuit. The controller causes an input current at the charging circuit to increase at a first rate of change in response to a start signal. When the controller detects an increase in a charging voltage at the power storage up to a first voltage at which driving of the first load is possible, the controller controls the charging circuit to cause the input current at the charging circuit to increase at a second rate of change lower than the first rate of change. The charging circuit is controlled by the controller to cause the input current to increase at the second rate of change, and the charging voltage at the power storage increases up to a second voltage at which driving of both the first load and the second load is possible.

Abstract: The information processing circuit 10 performs operations on layers in deep learning, and includes a product sum circuit 11 which performs a product-sum operation using input data and parameter values, and a parameter value output circuit 12 which outputs the parameter values, wherein the parameter value output circuit 12 is composed of a combinational circuit, and includes a first parameter value output circuit 13 manufactured in a way that a circuit configuration cannot be changed and a second parameter value output circuit 14 manufactured in a way that allows a circuit configuration to be changed.

Abstract: The information processing circuit 80 includes a first information processing circuit 81 that performs layer operations in deep learning, a second information processing circuit 82 that performs the layer operations in deep learning on input data by means of a programmable accelerator, and an integration circuit 83 integrates a calculation result of the first information processing circuit 81 with a calculation result of the second information processing circuit 82, and output an integration result, wherein the first information processing circuit 81 includes a parameter value output circuit 811 in which parameters of deep learning are circuited, and a sum-of-product circuit 812 that performs a sum-of-product operation using the input data and the parameters.

Abstract: The information processing circuit 10 performs operations on layers in deep learning, and includes a product sum circuit 11 which performs a product-sum operation using input data and parameter values, and a parameter value output circuit 12 which outputs the parameter values, wherein the parameter value output circuit 12 is composed of a combinational circuit.

Abstract: Each chip 70 includes weight storage unit for storing weights for each edge determined by learning under the condition that channels in a first layer that is a layer in a neural network and channels in a 0th layer that is a previous layer to the first layer are divided into groups whose number is equal to the number of the chips, respectively, the groups of the channels in the first layer and the groups of the channels in the 0th layer and the chips are associated, an edge is set between the channels belonging to corresponding groups, an edge is set between the channels belonging to non-corresponding groups under a restriction. The weight storage unit stores the weights determined for the edge between the channels, each of which corresponds to each chip including the weight storage unit, belonging to corresponding groups.

Abstract: The determining unit 72 divides channels in the 0th layer and channels in the first layer into groups whose number is equal to the number of chips that are included in an operation device executing an operation of the neural network using a learning result of the weight for each edge, respectively. The determining unit 72 determines association of the groups of the channels in the 0th layer and the groups of the channels in the first layer and the chips included in the operation device, and edges to be removed, and removes the edges to be removed. The weight assignment unit 73 stores the weights of the edges in the weight storage unit in the chip corresponding to the edge.

Abstract: A network system includes multiple processing units (21-1, 21-2, 22-1, 22-2) on each of which a desired virtual network function can be configured and a management apparatus that determines a communication path that connects the processing units so as to deploy a set of desired virtual network functions. At least one of the processing units includes a first communication interface that is connectable to any different processing unit and at least one second communication interface that is directly connectable to a predetermined different processing unit. The management apparatus determines the communication path for deploying the set of the desire virtual network functions, in accordance with respective connectable communication interfaces of the processing units.

Abstract: Provided is for reducing access latency. A high-level synthesis device includes feature quantity obtaining unit and implementation determination unit. Feature quantity obtaining unit obtains an access feature quantity including a feature quantity relating to communication between a plurality of modules by analyzing an access pattern in communication between the plurality of modules. Implementation determination unit determines an implementation method for communicating between the plurality of modules based on the obtained access feature quantity.

Abstract: A network system includes multiple processing units (21-1, 21-2, 22-1, 22-2) on each of which a desired virtual network function can be configured and a management apparatus that determines a communication path that connects the processing units so as to deploy a set of desired virtual network functions. At least one of the processing units includes a first communication interface that is connectable to any different processing unit and at least one second communication interface that is directly connectable to a predetermined different processing unit. The management apparatus determines the communication path for deploying the set of the desire virtual network functions, in accordance with respective connectable communication interfaces of the processing units.

Abstract: Provided is for reducing access latency. A high-level synthesis device includes feature quantity obtaining unit and implementation determination unit. Feature quantity obtaining unit obtains an access feature quantity including a feature quantity relating to communication between a plurality of modules by analyzing an access pattern in communication between the plurality of modules. Implementation determination unit determines an implementation method for communicating between the plurality of modules based on the obtained access feature quantity.

Abstract: Provided is an image processing device for performing noise removal in which a plurality of noise removal actions are combined while minimizing necessary resources.

Abstract: An information processing apparatus according to the present invention includes: a detection unit that detects detection information that is information indicating an external state of the apparatus; a communication unit that receives reception information that is a determination result given by another apparatus; and a control unit that calculates a first determination result that is a result acquired by determining a state of a surrounding of the apparatus based on the detection information and the reception information, transmits the first determination result to the another apparatus via the communication unit, and activates a necessary function for the detection unit or the communication unit and stops an unnecessary function thereof.

Abstract: Provided is an image processing device for performing noise removal in which a plurality of noise removal actions are combined while minimizing necessary resources.

Abstract: An information processing apparatus includes: a data cache apparatus including a cache memory; and a management apparatus including a large capacity memory whose capacity is larger than that of the cache memory, wherein the data cache apparatus includes a data cache control unit configured to control data in a predetermined condition stored in the cache memory to be located in the large capacity memory when a read request or a write request is received from outside the information processing apparatus, and wherein when the received request is a write request, the data cache control unit writes data to be written to the cache memory in accordance with the write request, and when the request is a read request, the data cache control unit writes data read in accordance with the read request to the cache memory.

Abstract: An information processing apparatus comprises: a processing data retention unit that retains structural information representing structure of a message, collation information for collation against text information contained in the message, and processing information representing a content(s) of processing for the text information; and a message processing unit that construes a received message in accordance with the structural information, and transforms, in case text information contained in the received message coincides with the collation information, the text information contained in the received message in accordance with the processing information, and outputs a message containing the transformed text information.

Abstract: A computation device includes a data path element (300) including a function processing unit (4000) that executes a computation specified in a function using input data included in an event (1000) as an argument; and a control path element (2000) that detects the event (1000) by use of a return value (ret) of the function. The function processing unit (4000) includes a data calculation unit (4001) that executes a computation and outputs a first result (d0); and a control comparison unit (4002) that outputs, to the control path element (2000), a result of comparison between the input data and data for specifying the event (1000), as the return value (ret).

Abstract: A computation device is provided with an event identification unit which receives a first event and outputs an event ID associated with an event type; a computation interim result retaining unit which receives the event ID and outputs a first computation interim result associated with the event ID; and a time-series computation processing unit which receives the first event and the first computation interim result, performs computation processing, and outputs a second event and a second computation interim result. The computation interim result retaining unit receives the second computation interim result, and retains the second computation interim result and the event ID in association with each other.

Abstract: A computation device includes a data path element (300) including a function processing unit (4000) that executes a computation specified in a function using input data included in an event (1000) as an argument; and a control path element (2000) that detects the event (1000) by use of a return value (ret) of the function. The function processing unit (4000) includes a data calculation unit (4001) that executes a computation and outputs a first result (d0); and a control comparison unit (4002) that outputs, to the control path element (2000), a result of comparison between the input data and data for specifying the event (1000), as the return value (ret).

Abstract: Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing signal, and logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that observes the signals, applies inputs, and observes outputs.