Abstract: A plug-in electronic clock being operated either by a commercial power source in a normal state or by a D.C. power source in case of a power failure, said electronic clock having means for generation of a pulse train used for a computation of time information in case of a power failure and means for stopping generation of the said pulse train in a case where the commercial power is active so as to prevent interference noise against radio receivers or television receivers, with a correct time information computation being assured when the commercial power source is recovered.

Abstract: An error correcting circuit utilizing a cube circuit for correcting errors in data having n+1 bits in accordance with the syndromes S.sub.1 and S.sub.3 from a check matrix H. The circuit comprises a generator for generating syndromes S.sub.1 and S.sub.3, means for providing (S.sub.1 -a.sub.i) based on the modulo 2 calculation for the i.sub.th line vector ##EQU1## OF THE CHECK MATRIX H corresponding to each data bit d.sub.1, means for multiplying (S.sub.1 -a.sub.i) three times, check means for checking the coincidence between (S.sub.1 -a.sub.i) and (S.sub.3 -a.sub.i.sup.3), and an inverting means for inverting the d.sub.i bit when the coincidence is detected.In the present invention, by utilizing a cube circuit the check circuit can be simplified.