Patents by Inventor Takashi Udagawa

Takashi Udagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240085844
    Abstract: An information processing apparatus includes a processor configured to: acquire factor information, which is information on a factor that influences an amount of volatilization of moisture supplied to each of recording media to be bound from the recording medium; and set an amount of moisture to be supplied to the recording medium on a basis of the factor information.
    Type: Application
    Filed: March 23, 2023
    Publication date: March 14, 2024
    Applicant: FUJIFILM Business Innovation Corp
    Inventors: Takashi OGINO, Nobuhide INABA, Kumiko TANAKA, Koji UDAGAWA
  • Publication number: 20230325180
    Abstract: A server in a team activity evaluation system includes, as its functions, a scoring module for specifying a team score (parameter) indicating an activity situation of an engineer team, based on various parameters indicating the activity situation of the engineer team, and a presentation module for presenting, to a user, the team score indicating the activity situation of the engineer team that has been specified, in association with time-series information.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 12, 2023
    Applicant: Findy Inc.
    Inventors: Masataka SATO, Hiroyuki ISHIKAWA, Takashi UDAGAWA, Chihaya TODA, Satoko TAKADA, Ryu FURUTA
  • Publication number: 20230289737
    Abstract: A server in an assumed annual income presentation system stores a user skill database for holding information of various parameters obtained by evaluating skills of each user as an engineer, and including, as its functions, a user job category reception module for receiving designation of a job category of a user who receives a presentation of an assumed annual income, and an assumed annual income specification module for specifying the assumed annual income for the user, based on the job category that has been designated by the user, a skill parameter related to the user, experience in the job category of each user, recruitment information of a company, or information of an annual income that has been received from each user, from the job category of the user.
    Type: Application
    Filed: May 18, 2023
    Publication date: September 14, 2023
    Applicant: Findy Inc.
    Inventors: Masataka SATO, Takashi UDAGAWA, Kazuto OHARA, Daishi MIYAMOTO, Toshiaki YANAGISAWA, Kihaya SUGIURA, Yuki SHIGA
  • Patent number: 9324912
    Abstract: A group III nitride semiconductor light-emitting element having a pn junction hetero structure composed of: an n-type aluminum gallium indium nitride layer; a light-emitting layer disposed contacting the n-type aluminum gallium indium nitride layer and including a gallium indium nitride layer containing crystals having a larger lattice constant than the n-type aluminum gallium indium nitride layer; and a p-type aluminum gallium indium nitride layer provided on the light-emitting layer. Further, the relative atomic concentrations of donor impurities at either interface of the light-emitting layer and within respective layers of the light-emitting element are specified herein.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: April 26, 2016
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Takashi Udagawa, Hiroshi Udagawa
  • Patent number: 9076913
    Abstract: A group III nitride semiconductor light-emitting element provided with: a semiconductor layer obtained by laminating a first semiconductor layer of a first conduction type, a light-emitting layer, and a second semiconductor layer of an opposite second conduction type; a first electrode connected to the first semiconductor layer; and a second electrode provided on the surface of the second semiconductor layer; the light-emitting layer including a first gallium indium nitride layer of a first indium composition, disposed on a side opposite the light extraction direction; a second gallium indium nitride layer of a second indium composition less than the first, disposed on the light extraction direction side from the first gallium indium nitride layer; and an intermediate layer containing a material of a smaller lattice constant than the materials constituting the first and second gallium indium nitride layers, provided between the first and second gallium indium nitride layers.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: July 7, 2015
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Takashi Udagawa, Hiroshi Udagawa
  • Patent number: 8389975
    Abstract: A Group III nitride semiconductor light-emitting device comprises a substrate (1) and a light-emitting layer (5) having the multiple quantum well structure that comprises barrier layers (5a) and well layers (5b) formed of a gallium-containing Group III nitride semiconductor material provided on the substrate. Each of the well layers constituting the multiple quantum well structure is made of a Group III nitride semiconductor layer to which acceptor impurities are added, and which has thicknesses different from one another and the same conductivity type as that of the barrier layer. The present invention can provide a Group III nitride semiconductor white light-emitting device which can enhance luminous intensity, can obtain high color rendering properties has a simple structure that can be easily formed without fine adjustment of a composition of a phosphor.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: March 5, 2013
    Assignee: Showa Denko K.K.
    Inventors: Tomo Kikuchi, Takashi Udagawa
  • Patent number: 8299451
    Abstract: A semiconductor light-emitting diode 20 is provided with a silicon single crystal substrate 201, an intervening layer 203 formed of a Group III nitride semiconductor and stacked on the silicon single crystal substrate 201, and a light-emitting part (205, 206, 207) formed with a p-n-junction hetero-junction structure and stacked on the intervening layer 203. The intervening layer 203 is formed of an aluminum-containing Group III nitride semiconductor. The intervening layer 203 and the light-emitting part (205, 206, 207) have interposed therebetween a superlattice structure 204 formed of a plurality of Group III nitride semiconductor layers that contain aluminum and have mutually different aluminum composition ratios. A DBR film formed of the superlattice structure 204 is enabled to excel in reflectance and enhance the light-emitting property.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: October 30, 2012
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Patent number: 8227790
    Abstract: In a Group III nitride semiconductor light-emitting device which includes a substrate (1) and a light-emitting layer (10) having a multiple quantum well structure including a barrier layer (11b, 12b), which is provided on a surface of the substrate and formed of a Group III nitride semiconductor, and a well layer (11a, 12a) formed of an indium-containing Group III nitride semiconductor, the light-emitting layer is constituted by stacking a plurality of multilayer portions (11, 12) which have one unit multilayer portion (11m) including the well layer and the barrier layer or two or more stacked unit multilayer portions (12m). When the multilayer portion (12) includes two or more unit multilayer portions (12m), the respective well or barrier layers have the same thickness and composition, and in the respective multilayer portions (11, 12), the barrier layers of the unit multilayer portions are different in thickness with respect to one another.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: July 24, 2012
    Assignee: Showa Denko K.K.
    Inventors: Tomo Kikuchi, Takashi Udagawa
  • Patent number: 8222674
    Abstract: Provided is a semiconductor device containing a silicon single crystal substrate 101, a silicon carbide layer 102 provided on a surface of the substrate, a Group III nitride semiconductor junction layer 103 provided in contact with the silicon carbide layer, and a superlattice-structured layer 104 constituted by Group III nitride semiconductors on the Group III nitride semiconductor junction layer. In this semiconductor device, the silicon carbide layer is a layer of a cubic system whose lattice constant exceeds 0.436 nm and is not more than 0.460 nm and which has a nonstoichiometric composition containing silicon abundantly in terms of composition, and the Group III nitride semiconductor junction layer has a composition of AlxGaYInzN1-?M? (0?X, Y, Z?1, X+Y+Z=1, 0??<1, M is a Group V element except nitrogen).
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: July 17, 2012
    Assignees: Showa Denko K.K., The Doshisha
    Inventors: Tadashi Ohachi, Takashi Udagawa
  • Patent number: 8216367
    Abstract: A method for producing a silicon carbide layer on a surface of a silicon substrate includes the step of irradiating the surface of the silicon substrate heated in a high vacuum at a temperature in a range of from 500° C. to 1050° C. with a hydrocarbon-based gas as well as an electron beam to form a cubic silicon carbide layer on the silicon substrate surface.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: July 10, 2012
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Patent number: 8134176
    Abstract: The present invention provides a light-emitting diode (10) including a substrate (101) made of a first conductive type silicon (Si) single crystal, a pn junction structured light-emitting section (40) composed of a III-group nitride semiconductor on the substrate, a first polarity ohmic electrode (107a) for the first conductive type semiconductor provided on the light-emitting section (40) and a second polarity ohmic electrode (108) for a second conductive type semiconductor on the same side as the light-emitting section (40) with respect to the substrate (101), wherein a second pn junction structure (30) is provided which is made up of a pn junction between the first conductive type semiconductor layer (102) and the second conductive type semiconductor layer (103) which is different from the pn junction structure of the light-emitting section (10).
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: March 13, 2012
    Assignee: Showa Denko K.K.
    Inventors: Ryouichi Takeuchi, Takashi Udagawa
  • Publication number: 20120007050
    Abstract: Provided is a semiconductor device containing a silicon single crystal substrate 101, a silicon carbide layer 102 provided on a surface of the substrate, a Group III nitride semiconductor junction layer 103 provided in contact with the silicon carbide layer, and a superlattice-structured layer 104 constituted by Group III nitride semiconductors on the Group III nitride semiconductor junction layer. In this semiconductor device, the silicon carbide layer is a layer of a cubic system whose lattice constant exceeds 0.436 nm and is not more than 0.460 nm and which has a nonstoichiometric composition containing silicon abundantly in terms of composition, and the Group III nitride semiconductor junction layer has a composition of AlxGaYInzN1-?M? (0?X, Y, Z?1, X+Y+Z=1, 0??<1, M is a Group V element except nitrogen).
    Type: Application
    Filed: September 19, 2011
    Publication date: January 12, 2012
    Applicants: THE DOSHISHA, SHOWA DENKO K.K.
    Inventors: Tadashi OHACHI, Takashi UDAGAWA
  • Patent number: 8084781
    Abstract: A compound semiconductor device (1) includes a compound semiconductor having a stacked structure (100) of a hexagonal single crystal layer (101), a boron phosphide-based semiconductor layer (102) formed on a surface of the hexagonal single crystal layer and a compound semiconductor layer (103) disposed on the boron phosphide-based semiconductor layer, and electrodes (108, 109) disposed on the stacked structure, wherein the boron phosphide-based semiconductor layer is formed of a hexagonal crystal disposed on a surface formed of a (1.1.-2.0.) crystal face of the hexagonal single crystal layer.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: December 27, 2011
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Patent number: 8071991
    Abstract: The present invention provides a light-emitting diode (10) including a first conductive type silicon single crystal substrate (101), a light-emitting section (40) including a first pn junction structure composed of a III-group nitride semiconductor on the substrate, a first polarity ohmic electrode (107b) provided on the light-emitting section, and a second polarity ohmic electrode (108) on the same side as the light-emitting section with respect to the substrate, wherein a second pn junction structure (30) is configured in a region which extends from the substrate to the light-emitting section, the substrate is provided with a light-reflecting hole (109) from the back surface of the substrate opposite to the side on which the light-emitting section of the substrate is provided toward the stacking direction, and the inner surface of the light-reflecting hole and the back surface of the substrate are coated with a metallic film (110).
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: December 6, 2011
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Patent number: 8043977
    Abstract: Provided is a semiconductor device containing a silicon single crystal substrate 101, a silicon carbide layer 102 provided on a surface of the substrate, a Group III nitride semiconductor junction layer 103 provided in contact with the silicon carbide layer, and a superlattice-structured layer 104 constituted by Group III nitride semiconductors on the Group III nitride semiconductor junction layer. In this semiconductor device, the silicon carbide layer is a layer of a cubic system whose lattice constant exceeds 0.436 nm and is not more than 0.460 nm and which has a nonstoichiometric composition containing silicon abundantly in terms of composition, and the Group III nitride semiconductor junction layer has a composition of AlxGaYInzN1-?M? (0?X, Y, Z?1, X+Y+Z=1, 0??<1, M is a Group V element except nitrogen).
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: October 25, 2011
    Assignees: Showa Denko K.K., The Doshisha
    Inventors: Tadashi Ohachi, Takashi Udagawa
  • Patent number: 8026525
    Abstract: A boron phosphide-based semiconductor light-emitting device includes a substrate of silicon single crystal, a first cubic boron phosphide-based semiconductor layer that is provided on a surface of the substrate and contains twins, a light-emitting layer that is composed of a hexagonal Group III nitride semiconductor and provided on the first cubic boron phosphide-based semiconductor layer and a second cubic boron phosphide-based semiconductor layer that is provided on the light-emitting layer, contains twins and has a conduction type different from that of the first cubic boron phosphide-based semiconductor layer.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: September 27, 2011
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Patent number: 7989926
    Abstract: A semiconductor device includes a substrate formed of a single crystal. a silicon carbide layer disposed on a surface of the single crystal substrate and an intermediate layer disposed on a surface of the silicon carbide layer and formed of a Group III nitride semiconductor, wherein the silicon carbide layer is formed of a cubic crystal stoichiometrically containing silicon copiously and the surface thereof has a (3×3) reconstruction structure.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: August 2, 2011
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Publication number: 20100288999
    Abstract: In a Group III nitride semiconductor light-emitting device which comprises a substrate (1) and a light-emitting layer (10) having a multiple quantum well structure comprising a barrier layer (11b, 12b), which is provided on a surface of the substrate and formed of a Group III nitride semiconductor, and a well layer (11a, 12a) formed of an indium-containing Group III nitride semiconductor, the light-emitting layer is constituted by stacking a plurality of multilayer portions (11, 12) which comprise one unit multilayer portion (11m) comprising the well layer and the barrier layer or two or more stacked unit multilayer portions (12m).
    Type: Application
    Filed: August 28, 2008
    Publication date: November 18, 2010
    Applicant: Showa Denko K.K.
    Inventors: Tomo Kikuchi, Takashi Udagawa
  • Publication number: 20100288998
    Abstract: A Group III nitride semiconductor light-emitting device comprises a substrate (1) and a light-emitting layer (5) having the multiple quantum well structure that comprises barrier layers (5a) and well layers (5b) formed of a gallium-containing Group III nitride semiconductor material provided on the substrate. Each of the well layers constituting the multiple quantum well structure is made of a Group III nitride semiconductor layer to which acceptor impurities are added, and which has thicknesses different from one another and the same conductivity type as that of the barrier layer. The present invention can provide a Group III nitride semiconductor white light-emitting device which can enhance luminous intensity, can obtain high color rendering properties has a simple structure that can be easily formed without fine adjustment of a composition of a phosphor.
    Type: Application
    Filed: August 28, 2008
    Publication date: November 18, 2010
    Applicant: SHOWA DENKO K.K.
    Inventors: Tomo Kikuchi, Takashi Udagawa
  • Patent number: 7790481
    Abstract: A pn-junction compound semiconductor light-emitting device is provided, which comprises a stacked structure including a light-emitting layer composed of an n-type or a p-type aluminum gallium indium phosphide and a light-permeable substrate for supporting the stacked structure, and the stacked structure and the light-permeable substrate being joined together, wherein the stacked structure includes an n-type or a p-type conductor layer, the conductor layer and the substrate are joined together, and the conductor layer is composed of a Group III-V compound semiconductor containing boron.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: September 7, 2010
    Assignee: Showa Denko K.K.
    Inventors: Ryouichi Takeuchi, Wataru Nabekura, Takashi Udagawa