Patents by Inventor Takashi Umegaki
Takashi Umegaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9277299Abstract: A line switching device includes multiple input ports to which signals are input and that include first input ports and second input ports different from the first input ports; multiple output ports that include given output ports; a branch unit that branches first signals input from the first input ports; and a switch that selectively outputs, among second signals input from the second input ports and branched signals branched from the first signals by the branch unit, signals that are to be switched to an output port among the given ports.Type: GrantFiled: August 10, 2012Date of Patent: March 1, 2016Assignee: FUJITSU LIMITEDInventors: Shigeo Tani, Takashi Umegaki
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Patent number: 9253553Abstract: A transmission apparatus includes: an assigning unit to assign a number to a group of concatenation information of leading and dependent data which are multicast or broadcast; a retrieval unit to retrieve the concatenation information of the leading data corresponding to the dependent data, the leading and dependent data having the same number; a regeneration unit to regenerate concatenation information of the dependent data in accordance with the concatenation information of the leading data; a storage unit to store switch information of the leading data, the switch information representing a switch which switches output destinations of the leading and dependent data; an information retrieval unit to refer to the storage unit in accordance with leading data information included in the concatenation information of the dependent data so as to retrieve switch information of the dependent data; and a switching unit to switch the output destination of the dependent data.Type: GrantFiled: December 14, 2012Date of Patent: February 2, 2016Assignee: FUJITSU LIMITEDInventors: Shigeo Tani, Takashi Umegaki
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Patent number: 8564355Abstract: There is provided a clock device including: a clock circuit to generate a plurality of clock signals, the clock circuit including a reset part for resetting generation of the clock signals; and a peripheral circuit operating based on the clock signals generated from the clock circuit, the peripheral circuit including: an error detection part for detecting an error in a process performed in the peripheral circuit by using the clock signals, and a determination part for determining whether to reset the clock circuit, based on information of the error detected by the error detection part.Type: GrantFiled: January 11, 2011Date of Patent: October 22, 2013Assignee: Fujitsu LimitedInventors: Shigeo Tani, Takashi Umegaki
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Publication number: 20130094805Abstract: A line switching device includes multiple input ports to which signals are input and that include first input ports and second input ports different from the first input ports; multiple output ports that include given output ports; a branch unit that branches first signals input from the first input ports; and a switch that selectively outputs, among second signals input from the second input ports and branched signals branched from the first signals by the branch unit, signals that are to be switched to an output port among the given ports.Type: ApplicationFiled: August 10, 2012Publication date: April 18, 2013Applicant: FUJITSU LIMITEDInventors: Shigeo TANI, Takashi Umegaki
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Patent number: 8295161Abstract: A network apparatus includes: an input interface unit; a first and second line switching units cross-connecting output signals from the input interface unit; an output interface unit including a selection unit selecting outputs from the first or second line switching units; and a CPU. The line switching units each include: a control signal generation unit storing setting data in a memory and generating a line switching control signal based on the setting data; a memory error detection processing unit detecting a memory error and outputting error information; and a main signal processing unit writing setting data into a buffer when an error is not detected, and holding setting data stored in the buffer when the error is detected, and which performs cross-connection processing according to the setting data stored in the buffer. The CPU controls the selection unit according to the error information.Type: GrantFiled: December 16, 2009Date of Patent: October 23, 2012Assignee: Fujitsu LimitedInventors: Ryoji Azumi, Takashi Umegaki, Shigeo Tani, Shosaku Yamasaki
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Publication number: 20110175653Abstract: There is provided a clock device including: a clock circuit to generate a plurality of clock signals, the clock circuit including a reset part for resetting generation of the clock signals; and a peripheral circuit operating based on the clock signals generated from the clock circuit, the peripheral circuit including: an error detection part for detecting an error in a process performed in the peripheral circuit by using the clock signals, and a determination part for determining whether to reset the clock circuit, based on information of the error detected by the error detection part.Type: ApplicationFiled: January 11, 2011Publication date: July 21, 2011Applicant: FUJITSU LIMITEDInventors: SHIGEO TANI, TAKASHI UMEGAKI
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Publication number: 20110170864Abstract: An interface device for demultiplexing, from a first frame in a transport network, a plurality of second frames multiplexed into the first frame is provided. The interface device includes an extractor configured to extract a plurality of data groups to constitute the first frame, and a second frame generator configured to create the second frames based on the plurality of data groups extracted by the extractor.Type: ApplicationFiled: January 10, 2011Publication date: July 14, 2011Applicant: FUJITSU LIMITEDInventors: Shigeo TANI, Hidenori Kiuchi, Takashi Umegaki, Ryoji Azumi, Shigehisa Sakahara
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Publication number: 20100158514Abstract: A network apparatus includes: an input interface unit; a first and second line switching units cross-connecting output signals from the input interface unit; an output interface unit including a selection unit selecting outputs from the first or second line switching units; and a CPU. The line switching units each include: a control signal generation unit storing setting data in a memory and generating a line switching control signal based on the setting data; a memory error detection processing unit detecting a memory error and outputting error information; and a main signal processing unit writing setting data into a buffer when an error is not detected, and holding setting data stored in the buffer when the error is detected, and which performs cross-connection processing according to the setting data stored in the buffer. The CPU controls the selection unit according to the error information.Type: ApplicationFiled: December 16, 2009Publication date: June 24, 2010Applicant: FUJITSU LIMITEDInventors: Ryoji AZUMI, Takashi Umegaki, Shigeo Tani, Shosaku Yamasaki
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Patent number: 7443843Abstract: An apparatus has a cross connection circuit, first switching sections located on the input side of the cross connection circuit to switch a presently-used transmission path and a reserve transmission path, and second switching sections located on the output side of the cross connection circuit to switch the presently-used transmission path and the reserve transmission path and comprises slot sections, first selecting section selectively connecting any one of the slot sections to the input side of the first switching section, second selecting section connecting the output side of the first switching section to the input side of the cross connection circuit, third selecting section selectively connecting the output side of the cross connection circuit to the input side of any of the second switching sections, and fourth selecting section connecting the output side of the second switching section to any one of the slot sections.Type: GrantFiled: April 6, 2005Date of Patent: October 28, 2008Assignee: Fujitsu LimitedInventors: Hiroyuki Matsuo, Mitsuhiro Kawaguchi, Shosaku Yamasaki, Takashi Umegaki, Koji Komatsu, Yoshimasa Itsuki
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Publication number: 20050195864Abstract: An apparatus has a cross connection circuit, first switching sections located on the input side of the cross connection circuit to switch a presently-used transmission path and a reserve transmission path, and second switching sections located on the output side of the cross connection circuit to switch the presently-used transmission path and the reserve transmission path and comprises slot sections, first selecting section selectively connecting any one of the slot sections to the input side of the first switching section, second selecting section connecting the output side of the first switching section to the input side of the cross connection circuit, third selecting section selectively connecting the output side of the cross connection circuit to the input side of any of the second switching sections, and fourth selecting section connecting the output side of the second switching section to any one of the slot sections.Type: ApplicationFiled: April 6, 2005Publication date: September 8, 2005Inventors: Hiroyuki Matsuo, Mitsuhiro Kawaguchi, Shosaku Yamasaki, Takashi Umegaki, Koji Komatsu, Yoshimasa Itsuki
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Patent number: 5589860Abstract: Both a cavity plate and a vibrating plate are made of polyether imide resin, and a polysulfone resin film having a thickness of 3 .mu.m is formed on one or both of the joining faces of the plates. The melt temperature of polysulfone resin is about 190.degree. C., and the heat deformation temperature of polyether imide resin is about 200.degree. C. When the cavity plate and the vibrating plate are contacted with each other through the polysulfone resin films and then heated at 190.degree. C. for one hour, therefore, the polysulfone resin films are fused to become a fused layer so that the plates are firmly joined. Since the heat deformation temperature of the cavity plate is 200.degree. C. which is higher by 10.degree. C. than the melt temperature (190.degree. C.) of the polysulfone resin films, the fusion does not cause ink flow paths of nozzles, etc. to be heat-deformed.Type: GrantFiled: August 10, 1994Date of Patent: December 31, 1996Assignee: Fuji Electric Co., Ltd.Inventors: Yoshinobu Sugata, Mikio Yamazaki, Takashi Umegaki
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Patent number: 5557437Abstract: An optical terminal system having self-monitoring function is disclosed, which includes a high-level group loopback section for internally looping back a serial electric signal, a low-level group loopback section for internally looping back a parallel electric signal, a self-loop section for connecting a receiver device and a transmitter device to loop an electric signal received by the receiver device directly to the transmitter device, and a self-monitoring controller for performing a self-monitoring test on respective components of the receiver device and transmitter device by using the self-loop section and either one of the high-level group loopback section and the low-level group loopback section. The optical terminal system can selfcheck the functions thereof through self-monitoring without depending on a network.Type: GrantFiled: June 7, 1995Date of Patent: September 17, 1996Assignee: Fujitsu LimitedInventors: Toshiharu Sakai, Yoshinori Nakamura, Takashi Umegaki, Nobuo Iguchi, Miki Hagino, Hiroaki Mori, Toshikazu Ota, Akihiko Oka, Kazuo Takatsu, Nobuyuki Nemoto
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Patent number: 5283576Abstract: A disparity detection circuit used in a signal decoder which decodes a 4-bit signal into an original 2-bit main signal and 1-bit service signal, from which the 4-bit signal is coded according to a coding rule which stipulates that an original 2-bit main signal and 1-bit service signal should be coded into a 4-bit signal with 1 additional bit added and with pre-determined disparity carrying, determines whether the 4-bit signal conforms to the coding rule and detects the disparity of the 4-bit signal which is determined as conforming to the coding rule.Type: GrantFiled: April 30, 1992Date of Patent: February 1, 1994Assignee: Fujitsu LimitedInventor: Takashi Umegaki