Abstract: There is provided a steel sheet having a chemical composition comprising, in mass %, C: 0.05 to 0.25%, Si: 0.2 to 2.0%, Mn: 1.2 to 3.0%, P: 0.030% or less, S: 0.050% or less, Al: 0.01 to 0.55%, N: 0.0100% or less, and Ti: 0.010 to 0.250%, with the balance: Fe and impurities, wherein a random intensity ratio of a texture in a near-surface portion of the steel sheet is 8.0 or less, and a minimum angle formed between a maximum strength orientation in a {110} pole figure of the texture and a normal direction of a rolled surface of the steel sheet is 10° or less.

Abstract: A semiconductor memory device including a plurality of stacked-capacitor type memory cells, each having a capacitor storing data and a transfer-gate transistor transferring data to the capacitor. The transistor includes a gate connected to a word line and formed by an insulating layer, and source and drain regions. Each of the memory cells has a first insulating layer covering the gate of the transfer-gate transistor.The capacitor in each memory cell includes a second insulating layer covering another word line adjacent to the one word line and having a larger thickness perpendicular to a plane of a substrate than that of the first insulating layer covering the gate, a second conductive layer which is in contact with one of the source and drain regions of the transistor, extends over the gate through the first insulating layer and covers the second insulating layer, a third insulating layer formed on the second conductive layer, and a third conductive layer extending over the third insulating layer.

Abstract: In a memory cell matrix region of a semiconductor memory device such as a dynamic RAM or a static RAM, wirings of the same material are distributed between different layers in such a manner that the upper wirings overlap the lower wirings. Accordingly, the width of the wirings can be increased for a semiconductor memory device having a high concentration and high integration.

Abstract: A method for producing a semiconductor device provided with a fuse including the steps of forming a fuse layer on an insulating layer formed on a semiconductor substrate, forming an interrupting layer covering the fuse layer and the insulating layer, forming an insulating protective layer covering the interrupting layer, selectively etching the protective layer, so as to form a window, with a suitable etchant which does not etch the interrupting layer, and etching the exposed interrupting layer to complete the window by which a portion of the the fuse layer and a portion of the insulating layer are exposed. The insulating layer is not removed so that the reliability of the semiconductor device will not deteriorate.

Abstract: A lower member of a cross wire structure formed in a semiconductor device, such as an MIS type semiconductor memory device, is provided with a structure of at least two layers of an impurity-containing polycrystalline semiconductor material according to the method disclosed. These layers are connected in parallel and their resistance is thus decreased. Furthermore, since these layers may be formed within insulating films over a semiconductor substrate, the degree of integration of the semiconductor device may be enhanced. The method for producing the cross electrodes allows simultaneous fabrication of other semiconductor devices, for instance MIS devices with components commonly fabricated with the cross electrode structures.