Patents by Inventor Takashi YAMAGIWA

Takashi YAMAGIWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power supply shutoff device and power supply shutoff method
    Patent number: 12007822
    Abstract: A power supply shutoff device includes a movable section, a driving section, a power supply device, a power distribution section, an electric power supply circuit, and a supply control section. The movable section is configured to travel on a traveling path provided along a board production line in which multiple board work machines, which perform a predetermined board work on a board, are installed side by side. The driving section is provided in the movable section and configured to cause the movable section to travel by using supply electric power supplied from the board work machine with non-contact power feeding. The supply control section is configured to stop a supply of the electric power to the electric power supply circuit when drive electric power for driving the board work machine is shut off in at least one board work machine among the multiple board work machines.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 11, 2024
    Assignee: FUJI CORPORATION
    Inventors: Shingo Fujimura, Sota Mizuno, Yusuke Saito, Takeshi Aoki, Masato Yamagiwa, Takashi Hirano, Shigenori Tanakamaru
  • BIST for performing parallel and serial test on memories
    Patent number: 11721407
    Abstract: According to a certain embodiment, the semiconductor integrated circuit includes a plurality of memories and a first control circuit configured to control the plurality of memories. The first control circuit includes a first state transition circuit configured to execute at least one of write control and read control during an operation of the plurality of memories; and a second state transition circuit connected to the first state transition circuit, the second state transition circuit capable of causing the first state transition circuit to sequentially execute tests of the plurality of memories.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: August 8, 2023
    Assignee: Kioxia Corporation
    Inventor: Takashi Yamagiwa
  • SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGN METHOD OF THE SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGN SUPPORT SYSTEM OF THE SEMICONDUCTOR INTEGRATED CIRCUIT, AND NON-TRANSITORY COMPUTER READABLE MEDIUM
    Publication number: 20220246228
    Abstract: According to a certain embodiment, the semiconductor integrated circuit includes a plurality of memories and a first control circuit configured to control the plurality of memories. The first control circuit includes a first state transition circuit configured to execute at least one of write control and read control during an operation of the plurality of memories; and a second state transition circuit connected to the first state transition circuit, the second state transition circuit capable of causing the first state transition circuit to sequentially execute tests of the plurality of memories.
    Type: Application
    Filed: September 1, 2021
    Publication date: August 4, 2022
    Applicant: Kioxia Corporation
    Inventor: Takashi YAMAGIWA