Patents by Inventor Takasuke Hayase

Takasuke Hayase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7940362
    Abstract: A display portion is divided by scan lines and signal lines into sections where pixels are provided. Contact holes each for connecting common wiring and a common electrode together are not formed for all the pixels, but decimated so as to be arranged in zigzags.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: May 10, 2011
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Shingo Saigo, Takasuke Hayase, Makoto Horinouchi, Hideto Motoshima, Akitoshi Maeda
  • Patent number: 7663146
    Abstract: An active matrix addressing LCD device having an active matrix substrate on which conductive lines are formed is provided, which suppress the AI hillock without complicating the structure of the lines and which decreases the electrical connection resistance increase at the terminals of the lines, thereby improving the connection reliability. The device comprises an active matrix substrate having a transparent, dielectric plate, thin-film transistors (TFTs) arranged on the plate, and pixel electrodes arranged on the plate. Gate electrodes of the TFTs and scan lines have a first multilevel conductive structure. Common electrodes and common lines may have the first multilevel conductive structure. Source and drain electrodes of the TFTs and signal lines may have a second multilevel conductive structures. Each of the first and second multilevel conductive structures includes a three-level TiN/Ti/Al or TiN/Al/Ti structure or a four-level TiN/Ti/AI/Ti structure.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: February 16, 2010
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Hiroaki Tanaka, Akira Fujita, Shigeru Kimura, Akitoshi Maeda, Takasuke Hayase
  • Patent number: 7609350
    Abstract: A display portion is divided by scan lines and signal lines into sections where pixels are provided. Contact holes each for connecting common wiring and a common electrode together are not formed for all the pixels, but decimated so as to be arranged in zigzags.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: October 27, 2009
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Shingo Saigo, Takasuke Hayase, Makoto Horinouchi, Hideto Motoshima, Akitoshi Maeda
  • Publication number: 20070013853
    Abstract: A display portion is divided by scan lines and signal lines into sections where pixels are provided. Contact holes each for connecting common wiring and a common electrode together are not formed for all the pixels, but decimated so as to be arranged in zigzags.
    Type: Application
    Filed: September 20, 2006
    Publication date: January 18, 2007
    Applicant: NEC LCD TECHNOLOGIES, LTD.
    Inventors: Shingo Saigo, Takasuke Hayase, Makoto Horinouchi, Hideto Motoshima, Akitoshi Maeda
  • Publication number: 20070013852
    Abstract: A display portion is divided by scan lines and signal lines into sections where pixels are provided. Contact holes each for connecting common wiring and a common electrode together are not formed for all the pixels, but decimated so as to be arranged in zigzags.
    Type: Application
    Filed: September 20, 2006
    Publication date: January 18, 2007
    Applicant: NEC LCD TECHNOLOGIES, LTD.
    Inventors: Shingo Saigo, Takasuke Hayase, Makoto Horinouchi, Hideto Motoshima, Akitoshi Maeda
  • Patent number: 7130009
    Abstract: A display portion is divided by scan lines and signal lines into sections where pixels are provided. Contact holes each for connecting common wiring and a common electrode together are not formed for all the pixels, but decimated so as to be arranged in zigzags.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: October 31, 2006
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Shingo Saigo, Takasuke Hayase, Makoto Horinouchi, Hideto Motoshima, Akitoshi Maeda
  • Patent number: 7110058
    Abstract: The method of fabricating a liquid crystal display device includes the steps of (a) fabricating a switching device on a substrate, (b) forming an interlayer insulating film on the substrate such that the switching device is covered with the interlayer insulating film, and (c) forming a transparent electrode on the interlayer insulating film, the transparent electrode being electrically connected to the switching device through the interlayer insulating film, the step (c) including (c1) depositing electrically conductive, transparent and amorphous material on the interlayer insulating film, (c2) patterning the material into the transparent electrode, and (c3) turning the transparent electrode into polysilicon by thermal annealing carried out after formation of an alignment film.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: September 19, 2006
    Assignee: NEC LCD Technologies
    Inventors: Takasuke Hayase, Keiko Yamada, Masami Yamashita, Shinichi Nakata, Akitoshi Maeda
  • Patent number: 7046314
    Abstract: The method of fabricating a liquid crystal display device includes the steps of (a) fabricating a switching device on a substrate, (b) forming an interlayer insulating film on the substrate such that the switching device is covered with the interlayer insulating film, and (c) forming a transparent electrode on the interlayer insulating film, the transparent electrode being electrically connected to the switching device through the interlayer insulating film, the step (c) including (c1) depositing electrically conductive, transparent and amorphous material on the interlayer insulating film, (c2) patterning the material into the transparent electrode, and (c3) turning the transparent electrode into polysilicon by thermal annealing carried out after formation of an alignment film.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: May 16, 2006
    Assignee: NEC LCD Technologies Ltd.
    Inventors: Takasuke Hayase, Keiko Yamada, Masami Yamashita, Shinichi Nakata, Akitoshi Maeda
  • Patent number: 7012657
    Abstract: The method of fabricating a liquid crystal display device includes the steps of (a) fabricating a switching device on a substrate, (b) forming an interlayer insulating film on the substrate such that the switching device is covered with the interlayer insulating film, and (c) forming a transparent electrode on the interlayer insulating film, the transparent electrode being electrically connected to the switching device through the interlayer insulating film, the step (c) including (c1) depositing electrically conductive, transparent and amorphous material on the interlayer insulating film, (c2) patterning the material into the transparent electrode, and (c3) turning the transparent electrode into polysilicon by thermal annealing carried out after formation of an alignment film.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: March 14, 2006
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Takasuke Hayase, Keiko Yamada, Masami Yamashita, Shinichi Nakata, Akitoshi Maeda
  • Publication number: 20050250260
    Abstract: The method of fabricating a liquid crystal display device includes the steps of (a) fabricating a switching device on a substrate, (b) forming an interlayer insulating film on the substrate such that the switching device is covered with the interlayer insulating film, and (c) forming a transparent electrode on the interlayer insulating film, the transparent electrode being electrically connected to the switching device through the interlayer insulating film, the step (c) including (c1) depositing electrically conductive, transparent and amorphous material on the interlayer insulating film, (c2) patterning the material into the transparent electrode, and (c3) turning the transparent electrode into polysilicon by thermal annealing carried out after formation of an alignment film.
    Type: Application
    Filed: May 20, 2005
    Publication date: November 10, 2005
    Applicant: NEC LCD TECHNOLOGIES, LTD.
    Inventors: Takasuke Hayase, Keiko Yamada, Masami Yamashita, Shinichi Nakata, Akitoshi Maeda
  • Publication number: 20050227399
    Abstract: The method of fabricating a liquid crystal display device includes the steps of (a) fabricating a switching device on a substrate, (b) forming an interlayer insulating film on the substrate such that the switching device is covered with the interlayer insulating film, and (c) forming a transparent electrode on the interlayer insulating film, the transparent electrode being electrically connected to the switching device through the interlayer insulating film, the step (c) including (c1) depositing electrically conductive, transparent and amorphous material on the interlayer insulating film, (c2) patterning the material into the transparent electrode, and (c3) turning the transparent electrode into polysilicon by thermal annealing carried out after formation of an alignment film.
    Type: Application
    Filed: May 20, 2005
    Publication date: October 13, 2005
    Applicant: NEC LCD TECHNOLOGIES, LTD.
    Inventors: Takasuke Hayase, Keiko Yamada, Masami Yamashita, Shinichi Nakata, Akitoshi Maeda
  • Patent number: 6891196
    Abstract: An active matrix substrate of a channel protection type having a gate electrode, a drain electrode and a pixel electrode is isolated in each layer by insulating films. The active matrix substrate is to be prepared by four masks. A gate electrode layer, a gate insulating film and an a-Si layer are processed to the same shape on a transparent insulating substrate to form a gate electrode layer and a TFF area. A drain electrode layer is formed by a first passivation film with the first passivation film formed as an upper layer. In a second passivation film, formed above the first passivation film, are bored a first opening through the first and second passivation films and a second opening through the second passivation film. A wiring connection layer is formed by ITO provided as an uppermost layer.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: May 10, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Hiroaki Tanaka, Hirotaka Yamaguchi, Wakahiko Kaneko, Michiaki Sakamoto, Satoshi Ihida, Takasuke Hayase, Tae Yoshikawa, Hiroshi Kanou
  • Patent number: 6890783
    Abstract: An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and n+ amorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the n+ amorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: May 10, 2005
    Assignee: NEC LCD Technologies, LTD.
    Inventors: Shigeru Kimura, Takahiko Watanabe, Tae Yoshikawa, Hiroyuki Uchida, Shusaku Kido, Shinichi Nakata, Tsutomu Hamada, Hisanobu Shimodouzono, Satoshi Doi, Toshihiko Harano, Akitoshi Maeda, Satoshi Ihida, Hiroaki Tanaka, Takasuke Hayase, Shouichi Kuroha, Hirofumi Ihara, Kazushige Takechi
  • Patent number: 6788355
    Abstract: A method for fabricating an active matrix LCD panel for use in an active matrix LCD device includes the step of forming a passivation layer acting as a channel protection layer for protecting an amorphous silicon active layer, thereby reducing the number of photolithographic steps. A transparent conductive film is used for forming a gate electrode and a pixel electrode before formation of an amorphous silicon film for the TFTs.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: September 7, 2004
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Satoshi Ihida, Hirotaka Yamaguchi, Hiroaki Tanaka, Takasuke Hayase, Hiroshi Kanou, Wakahiko Kaneko, Tae Miyahara, Michiaki Sakamoto, Shinichi Nakata
  • Patent number: 6740596
    Abstract: The photolithography processes for connecting the first conductive film pattern, which is a lower layer such as a gate electrode of a TFT, to a second conductive film pattern, which is an upper layer such as a source/drain electrode of a TFT are reduced by utilizing laminated films and a resist pattern formed thereon having different film thicknesses. Laminated films constituting the source/drain electrode are formed by depositing films on an insulating substrate on which the first conductive film pattern is formed, and the resist pattern is formed on the top layer of the laminated films, and then utilizing the film thickness difference of the resist pattern and the film composition of the laminated films, the short circuited wiring between the gate electrode and the source/drain electrode for an Electro-Static-Discharge protection circuit of the active matrix substrate can be formed by less photolithography processes than that in the manufacturing of the conventional active matrix substrate.
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: May 25, 2004
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Takasuke Hayase, Hiroaki Tanaka, Shusaku Kido, Toshihiko Harano
  • Publication number: 20040084672
    Abstract: An active matrix substrate of a channel protection type having a gate electrode, a drain electrode and a pixel electrode isolated from one another from layer to layer by insulating films. The active matrix substrate is to be prepared by four masks. A gate electrode layer, a gate insulating film and an a-Si layer are processed to the same shape on a transparent insulating substrate to form a gate electrode layer (102 of FIG. 6) and a TFF area. A drain electrode layer (106 of FIG. 6) is formed by a first passivation film (105 of FIG. 6) via a first passivation film (105 of FIG. 6) formed as an upper layer. In a second passivation film (107 of FIG. 6) formed above it are bored an opening through the first and second passivation films and an opening through the second passivation film. A wiring connection layer is formed by ITO (108 of FIG. 6) provided as an uppermost layer.
    Type: Application
    Filed: July 11, 2003
    Publication date: May 6, 2004
    Applicant: NEC LCD Technologies, Ltd.
    Inventors: Hiroaki Tanaka, Hirotaka Yamaguchi, Wakahiko Kaneko, Michiaki Sakamoto, Satoshi Ihida, Takasuke Hayase, Tae Yoshikawa, Hiroshi Kanou
  • Publication number: 20040085489
    Abstract: The method of fabricating a liquid crystal display device includes the steps of (a) fabricating a switching device on a substrate, (b) forming an interlayer insulating film on the substrate such that the switching device is covered with the interlayer insulating film, and (c) forming a transparent electrode on the interlayer insulating film, the transparent electrode being electrically connected to the switching device through the interlayer insulating film, the step (c) including (c1) depositing electrically conductive, transparent and amorphous material on the interlayer insulating film, (c2) patterning the material into the transparent electrode, and (c3) turning the transparent electrode into polysilicon by thermal annealing carried out after formation of an alignment film.
    Type: Application
    Filed: October 27, 2003
    Publication date: May 6, 2004
    Applicant: NEC LCD TECHNOLOGIES, LTD.
    Inventors: Takasuke Hayase, Keiko Yamada, Masami Yamashita, Shinichi Nakata, Akitoshi Maeda
  • Publication number: 20040070718
    Abstract: A display portion is divided by scan lines and signal lines into sections where pixels are provided. Contact holes each for connecting common wiring and a common electrode together are not formed for all the pixels, but decimated so as to be arranged in zigzags.
    Type: Application
    Filed: September 15, 2003
    Publication date: April 15, 2004
    Applicant: NEC LCD TECHNOLOGIES, LTD.
    Inventors: Shingo Saigo, Takasuke Hayase, Makoto Horinouchi, Hideto Motoshima, Akitoshi Maeda
  • Patent number: 6674093
    Abstract: An active matrix substrate of a channel protection type having a gate electrode, a drain electrode and a pixel electrode isolated from one another from layer to layer by insulating films. The active matrix substrate is to be prepared by four masks. A gate electrode layer, a gate insulating film and an a-Si layer are processed to the same shape on a transparent insulating substrate to form a gate electrode layer (102 of FIG. 6) and a TFF area. A drain electrode layer (106 of FIG. 6) is formed by a first passivation film (105 of FIG. 6) via a first passivation film (105 of FIG. 6) formed as an upper layer. In a second passivation film (107 of FIG. 6) formed above it are bored an opening through the first and second passivation films and an opening through the second passivation film. A wiring connection layer is formed by ITO (108 of FIG. 6) provided as an uppermost layer.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: January 6, 2004
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Hiroaki Tanaka, Hirotaka Yamaguchi, Wakahiko Kaneko, Michiaki Sakamoto, Satoshi Ihida, Takasuke Hayase, Tae Yoshikawa, Hiroshi Kanou
  • Patent number: 6632696
    Abstract: An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and n+ amorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the n+ amorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: October 14, 2003
    Assignee: NEC Corporation
    Inventors: Shigeru Kimura, Takahiko Watanabe, Tae Yoshikawa, Hiroyuki Uchida, Shusaku Kido, Shinichi Nakata, Tsutomu Hamada, Hisanobu Shimodouzono, Satoshi Doi, Toshihiko Harano, Akitoshi Maeda, Satoshi Ihida, Hiroaki Tanaka, Takasuke Hayase, Shouichi Kuroha, Hirofumi Ihara, Kazushige Takechi