Patents by Inventor Takato Shimoyama
Takato Shimoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7203113Abstract: Disclosed is a semiconductor storage device in which control is performed in such a manner that if the refresh operation is not being performed when a chip-select signal undergoes a transition from an inactive (standby) state to an active state, read or write access is executed immediately and if the refresh operation is in progress when the chip-select signal undergoes a transition from the inactive state to the active state, a wait signal for causing read or write access to wait is generated by a wait generating circuit.Type: GrantFiled: March 28, 2005Date of Patent: April 10, 2007Assignee: NEC Electronics CorporationInventors: Hiroyuki Takahashi, Takato Shimoyama, Takuya Hirota
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Patent number: 7184322Abstract: A semiconductor memory device has common terminals shared between a part or all of address terminals for receiving n bits of an address signal and data terminals for outputting a data signal with its bit width of n bits or less and dedicated address terminals for receiving m bits of the address signal, wherein at the time of a read, after the n bits of the address signal have been input, a plurality of data signals within a selected page are consecutively read out through the common terminals using the m bits of the address signal input from the dedicated address terminals.Type: GrantFiled: November 12, 2004Date of Patent: February 27, 2007Assignee: NEC Electronics CorporationInventors: Hiroyuki Takahashi, Takato Shimoyama, Takuya Hirota
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Patent number: 7145812Abstract: There is provided a method of entry of an operation mode of a semiconductor memory during operations without need of any specific timing specification and with effective suppression to any erroneous entry. If read cycles for plural addresses are continued, then a request for entry of operation mode is accepted (steps S1 and S2). In write cycles following to those read cycles, an operation mode to be entered is decided based on data externally designated, wherein in the first write cycle, the kind of the operation mode is set, and then in the next write cycle, conditions for the operation mode are set for the entry of the operation mode of the semiconductor memory.Type: GrantFiled: May 20, 2005Date of Patent: December 5, 2006Assignee: NEC Electronics CorporationInventors: Hiroyuki Takahashi, Takato Shimoyama, Takashi Kusakari
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Publication number: 20050219930Abstract: Disclosed is a semiconductor storage device in which control is performed in such a manner that if the refresh operation is not being performed when a chip-select signal undergoes a transition from an inactive (standby) state to an active state, read or write access is executed immediately and if the refresh operation is in progress when the chip-select signal undergoes a transition from the inactive state to the active state, a wait signal for causing read or write access to wait is generated by a wait generating circuit.Type: ApplicationFiled: March 28, 2005Publication date: October 6, 2005Inventors: Hiroyuki Takahashi, Takato Shimoyama, Takuya Hirota
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Publication number: 20050216676Abstract: There is provided a method of entry of an operation mode of a semiconductor memory during operations without need of any specific timing specification and with effective suppression to any erroneous entry. If read cycles for plural addresses are continued, then a request for entry of operation mode is accepted (steps S1 and S2). In write cycles following to those read cycles, an operation mode to be entered is decided based on data externally designated, wherein in the first write cycle, the kind of the operation mode is set, and then in the next write cycle, conditions for the operation mode are set for the entry of the operation mode of the semiconductor memory.Type: ApplicationFiled: May 20, 2005Publication date: September 29, 2005Inventors: Hiroyuki Takahashi, Takato Shimoyama, Takashi Kusakari
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Patent number: 6925016Abstract: There is provided a method of entry of an operation mode of a semiconductor memory during operations without need of any specific timing specification and with effective suppression to any erroneous entry. If read cycles for plural addresses are continued, then, a request for entry of operation mode is accepted. In write cycles following to those read cycles, an operation mode to be entered is decided based on data externally designated, wherein in the first write cycle, the kind of the operation mode is set, and then in the next write cycle, conditions for the operation mode are set for the entry of the operation mode of the semiconductor memory.Type: GrantFiled: January 30, 2002Date of Patent: August 2, 2005Assignee: NEC Electronics CorporationInventors: Hiroyuki Takahashi, Takato Shimoyama, Takashi Kusakari
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Publication number: 20050105380Abstract: A semiconductor memory device has common terminals shared between a part or all of address terminals for receiving n bits of an address signal and data terminals for outputting a data signal with its bit width of n bits or less and dedicated address terminals for receiving m bits of the address signal, wherein at the time of a read, after the n bits of the address signal have been input, a plurality of data signals within a selected page are consecutively read out through the common terminals using the m bits of the address signal input from the dedicated address terminals.Type: ApplicationFiled: November 12, 2004Publication date: May 19, 2005Applicant: NEC ELECTRONICS CORPORATIONInventors: Hiroyuki Takahashi, Takato Shimoyama, Takuya Hirota
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Publication number: 20040080993Abstract: There is provided a method of entry of an operation mode of a semiconductor memory during operations without need of any specific timing specification and with effective suppression to any erroneous entry.Type: ApplicationFiled: August 1, 2003Publication date: April 29, 2004Inventors: Hiroyuki Takahashi, Takato Shimoyama, Takashi Kusakari
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Patent number: 6556482Abstract: According to the disclosed embodiments, a semiconductor memory device may include an address register circuit (406) and data register circuit (411) that can store a write address and write data from one write operation and output the stored write address and write data during a subsequent write operation. In a dynamic random access memory (DRAM) embodiment (400), a precharge and/or refresh operation may follow the writing of previously stored write data. Such an arrangement may reduce and/or eliminate a read after write timing requirement (TWR), which can improve the operating speed of the semiconductor memory device.Type: GrantFiled: June 1, 2001Date of Patent: April 29, 2003Assignee: NEC Electronics CorporationInventors: Takato Shimoyama, Hiroyuki Takahashi
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Patent number: 6356473Abstract: According to one embodiment, an asynchronous static random access memory (SRAM) circuit (100) can provide reduced power consumption and high-speed access. An SRAM circuit (100) may include address registers (122 and 128) that can store a write address from one write operation and output the stored write address during a subsequent write operation. A data register (138) may also be included that can store write data from one write operation and output the stored write data during a subsequent write operation. Memory cells of a memory cell array (102) may be selected according to a pulse word signal PW. A pulse word signal PW can be generated in response to transitions in an address and transitions in a write enable signal /WE. Hit address comparators (220) within address registers (122 and 128) in combination with a hit AND gate (136) can activate a HIT ALL signal when a stored write address matches an applied read address.Type: GrantFiled: June 23, 2000Date of Patent: March 12, 2002Assignee: NEC CorporationInventor: Takato Shimoyama
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Publication number: 20010024382Abstract: According to the disclosed embodiments, a semiconductor memory device may include an address register circuit (406) and data register circuit (411) that can store a write address and write data from one write operation and output the stored write address and write data during a subsequent write operation. In a dynamic random access memory (DRAM) embodiment (400), a precharge and/or refresh operation may follow the writing of previously stored write data. Such an arrangement may reduce and/or eliminate a read after write timing requirement (TWR), which can improve the operating speed of the semiconductor memory device.Type: ApplicationFiled: June 1, 2001Publication date: September 27, 2001Inventors: Takato Shimoyama, Hiroyuki Takahashi