Abstract: A semiconductor device of trench gate type is formed of a group III nitride semiconductor. The semiconductor device has a substrate, a first layer, a second layer, and a third layer accumulated in this order, and further has a trench penetrating through the third layer and the second layer and reaching the first layer. A side surface of the trench, exposed to the second layer, is perpendicular to a main surface of the substrate. A side surface of the trench, exposed to the third layer, includes a first region which is perpendicular to the main surface of the substrate, and a second region above the first region, which is inclined with respect to the main surface of the substrate. A cross-sectional area of the trench at the second region in a plane parallel to a bottom surface of the trench increases from a bottom toward an upper of the trench.

Abstract: A semiconductor device comprises: a nitride semiconductor layer; an oxide insulating film formed to contact the nitride semiconductor layer; and a gate electrode formed to contact the oxide insulating film and made of metal nitride in a crystal orientation including at least one of the (200) orientation and the (220) orientation.

Abstract: A semiconductor device comprises: a nitride semiconductor layer; an oxide insulating film formed to contact the nitride semiconductor layer; and a gate electrode formed to contact the oxide insulating film and made of metal nitride in a crystal orientation including at least one of the (200) orientation and the (220) orientation.

Abstract: A nonvolatile semiconductor memory comprises a memory cell array in which a plurality of memory cell transistors capable of storing data according to a threshold voltage; a row decoder having a plurality of transfer MOS transistors connected at first ends to a plurality of word lines which are respectively connected to control gate electrodes of the plurality of memory cell transistors; and a word line driver which selects supplied voltages and supplies the selected voltages to second ends of the plurality of transfer MOS transistors. The nonvolatile semiconductor memory further comprises a voltage generation circuit which supplies voltages to the word line driver; and a control circuit which controls operation of the row decoder, the word line driver and the voltage generation circuit.

Abstract: According to one embodiment, a semiconductor memory device includes a memory, and a data transfer section configured to perform data transfer from and to the memory, and having a first mode to transfer data with a first bit width and a second mode to transfer data with a second bit width. The data transfer section includes a first latch circuit configured to hold first data read from the memory, a second latch circuit configured to hold second data having the first bit width of the first data in the first mode, and to hold third data having the second bit width of the first data in the second mode, and data bus connecting the first latch circuit to the second latch circuit and shared by the first and second modes.

Abstract: A nonvolatile semiconductor memory comprises a memory cell array in which a plurality of memory cell transistors capable of storing data according to a threshold voltage; a row decoder having a plurality of transfer MOS transistors connected at first ends to a plurality of word lines which are respectively connected to control gate electrodes of the plurality of memory cell transistors; and a word line driver which selects supplied voltages and supplies the selected voltages to second ends of the plurality of transfer MOS transistors. The nonvolatile semiconductor memory further comprises a voltage generation circuit which supplies voltages to the word line driver; and a control circuit which controls operation of the row decoder, the word line driver and the voltage generation circuit.