Patents by Inventor Takatoshi MANABE
Takatoshi MANABE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11411494Abstract: A first current mirror circuit is provided between a first transistor and a power supply line to return a current that flows to the first transistor. A second current mirror circuit returns an output current from the first current mirror circuit, and generates a starting current. An inverter has an input connected to a node, and an output connected to a control terminal of the first transistor. A first current source generates a first current when a power supply voltage has exceeded a first threshold value. A third current mirror circuit draws a current proportional to the first current from an input side of the second current mirror circuit. A second current source supplies a second current to the node when the power supply voltage has exceeded a second threshold value.Type: GrantFiled: January 28, 2021Date of Patent: August 9, 2022Assignee: ROHM Co., LTD.Inventors: Naohiro Nomura, Takatoshi Manabe
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Patent number: 11329619Abstract: Disclosed herein is an operational amplifier including a non-inverting input terminal, an inverting input terminal, a P-type metal oxide semiconductor input differential pair, a first input tail current source, an N-type metal oxide semiconductor input differential pair, a second input tail current source, an output stage, a first correction circuit, and a second correction circuit. The first correction circuit and the second correction circuit operate over an operation region of the P-type metal oxide semiconductor input differential pair, an operation region of the N-type metal oxide semiconductor input differential pair, and a transition region in which both the P-type metal oxide semiconductor input differential pair and the N-type metal oxide semiconductor input differential pair operate.Type: GrantFiled: February 17, 2021Date of Patent: May 10, 2022Assignee: ROHM Co., LTD.Inventors: Naohiro Nomura, Takatoshi Manabe
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Publication number: 20210265962Abstract: Disclosed herein is an operational amplifier including a non-inverting input terminal, an inverting input terminal, a P-type metal oxide semiconductor input differential pair, a first input tail current source, an N-type metal oxide semiconductor input differential pair, a second input tail current source, an output stage, a first correction circuit, and a second correction circuit. The first correction circuit and the second correction circuit operate over an operation region of the P-type metal oxide semiconductor input differential pair, an operation region of the N-type metal oxide semiconductor input differential pair, and a transition region in which both the P-type metal oxide semiconductor input differential pair and the N-type metal oxide semiconductor input differential pair operate.Type: ApplicationFiled: February 17, 2021Publication date: August 26, 2021Applicant: ROHM Co., LTD.Inventors: Naohiro Nomura, Takatoshi Manabe
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Publication number: 20210242772Abstract: A first current mirror circuit is provided between a first transistor and a power supply line to return a current that flows to the first transistor. A second current mirror circuit returns an output current from the first current mirror circuit, and generates a starting current. An inverter has an input connected to a node, and an output connected to a control terminal of the first transistor. A first current source generates a first current when a power supply voltage has exceeded a first threshold value. A third current mirror circuit draws a current proportional to the first current from an input side of the second current mirror circuit. A second current source supplies a second current to the node when the power supply voltage has exceeded a second threshold value.Type: ApplicationFiled: January 28, 2021Publication date: August 5, 2021Inventors: Naohiro Nomura, Takatoshi Manabe
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Patent number: 10848115Abstract: There is provided a chopper stabilized amplifier with an input bias current reduced. The chopper stabilized amplifier includes a main amplifier and a correction circuit. The correction circuit includes a second gm amplifier of a full differential type. A first selector and the second gm amplifier are coupled to each other without DC blocking capacitors. The differential input state of the second gm amplifier is configured with a depletion-type transistor.Type: GrantFiled: March 13, 2019Date of Patent: November 24, 2020Assignee: ROHM CO., LTD.Inventors: Naohiro Nomura, Takatoshi Manabe
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Patent number: 10812029Abstract: An operational amplifier includes a gain boost circuit. The gain boost circuit includes a first differential gm amplifier of a first stage, and a second differential gm amplifier of a post stage. Phase compensation capacitors are provided between inputs and outputs of a system of the second differential gm amplifier.Type: GrantFiled: December 26, 2018Date of Patent: October 20, 2020Assignee: ROHM CO., LTD.Inventors: Naohiro Nomura, Takatoshi Manabe
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Patent number: 10754369Abstract: A first transistor and a second transistor have control terminals coupled to each other. A current mirror circuit supplies a current having the same amount as that of a current Iref flowing through a first path including the second transistor to a second path including the first transistor and supplies a current having a predetermined number of times m of a current amount of the current Iref of the first path to a third path separate from the second path. The third transistor and a fourth transistor are provided on the third path. The third transistor has a source coupled to one end of the first transistor, and the fourth transistor has a gate coupled to a gate of the third transistor. A resistor is provided between a source of the fourth transistor and one end of the second transistor.Type: GrantFiled: August 8, 2019Date of Patent: August 25, 2020Assignee: ROHM CO., LTD.Inventors: Naohiro Nomura, Takatoshi Manabe
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Patent number: 10586605Abstract: A sample hold circuit includes at least one capacitor CS and at least one complementary metal-oxide semiconductor (CMOS) switch. The CMOS switch includes an N-channel metal-oxide semiconductor (NMOS) transistor and a P-channel metal-oxide semiconductor (PMOS) transistor connected in parallel. A high level of a gate signal VGN of the NMOS transistor is adjusted to a voltage level VREG lower than a power supply voltage VDD of a chip on which the CMOS switch is integrated.Type: GrantFiled: November 19, 2018Date of Patent: March 10, 2020Assignee: ROHM CO., LTD.Inventors: Naohiro Nomura, Takatoshi Manabe
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Publication number: 20200050231Abstract: A first transistor and a second transistor have control terminals coupled to each other. A current mirror circuit supplies a current having the same amount as that of a current Iref flowing through a first path including the second transistor to a second path including the first transistor and supplies a current having a predetermined number of times m of a current amount of the current Iref of the first path to a third path separate from the second path. The third transistor and a fourth transistor are provided on the third path. The third transistor has a source coupled to one end of the first transistor, and the fourth transistor has a gate coupled to a gate of the third transistor. A resistor is provided between a source of the fourth transistor and one end of the second transistor.Type: ApplicationFiled: August 8, 2019Publication date: February 13, 2020Inventors: Naohiro NOMURA, Takatoshi MANABE
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Patent number: 10554179Abstract: A differential circuit includes a differential pair and a back gate bias circuit. The differential circuit includes a first MOS transistor and a second MOS transistor provided between a first power supply line, to which a first power supply voltage is applied, and a second power supply line, to which a second power supply voltage is applied. The back gate bias circuit applies a bias voltage closer to the first power supply voltage than source potentials of the first MOS transistor and the second MOS transistor to back gates of the first MOS transistor and the second MOS transistor.Type: GrantFiled: August 6, 2018Date of Patent: February 4, 2020Assignee: ROHM CO., LTD.Inventors: Naohiro Nomura, Sachito Horiuchi, Kunihiko Iwamoto, Takatoshi Manabe
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Publication number: 20190288656Abstract: There is provided a chopper stabilized amplifier with an input bias current reduced. The chopper stabilized amplifier includes a main amplifier and a correction circuit. The correction circuit includes a second gm amplifier of a full differential type. A first selector and the second gm amplifier are coupled to each other without DC blocking capacitors. The differential input state of the second gm amplifier is configured with a depletion-type transistor.Type: ApplicationFiled: March 13, 2019Publication date: September 19, 2019Inventors: Naohiro NOMURA, Takatoshi MANABE
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Publication number: 20190199304Abstract: An operational amplifier includes a gain boost circuit. The gain boost circuit includes a first differential gm amplifier of a first stage, and a second differential gm amplifier of a post stage. Phase compensation capacitors are provided between inputs and outputs of a system of the second differential gm amplifier.Type: ApplicationFiled: December 26, 2018Publication date: June 27, 2019Inventors: Naohiro Nomura, Takatoshi Manabe
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Publication number: 20190156906Abstract: A sample hold circuit includes at least one capacitor CS and at least one complementary metal-oxide semiconductor (CMOS) switch. The CMOS switch includes an N-channel metal-oxide semiconductor (NMOS) transistor and a P-channel metal-oxide semiconductor (PMOS) transistor connected in parallel. A high level of a gate signal VGN of the NMOS transistor is adjusted to a voltage level VREG lower than a power supply voltage VDD of a chip on which the CMOS switch is integrated.Type: ApplicationFiled: November 19, 2018Publication date: May 23, 2019Inventors: Naohiro NOMURA, Takatoshi MANABE
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Publication number: 20190052231Abstract: A differential circuit includes a differential pair and a back gate bias circuit. The differential circuit includes a first MOS transistor and a second MOS transistor provided between a first power supply line, to which a first power supply voltage is applied, and a second power supply line, to which a second power supply voltage is applied. The back gate bias circuit applies a bias voltage closer to the first power supply voltage than source potentials of the first MOS transistor and the second MOS transistor to back gates of the first MOS transistor and the second MOS transistor.Type: ApplicationFiled: August 6, 2018Publication date: February 14, 2019Inventors: Naohiro NOMURA, Sachito HORIUCHI, Kunihiko IWAMOTO, Takatoshi MANABE