Abstract: According to one embodiment, an ultrasonic probe includes a probe unit and cooling unit. The probe unit is obtained by arranging, in a housing, a transducer unit which transmits and receives ultrasonic waves with an object to be examined, an electronic circuit unit which is connected to the transducer unit and performs electrical signal processing, and a heat transfer member which is made of a material having a heat transfer coefficient higher than that of the electronic circuit unit, and transfers heat of the electronic circuit unit to a housing surface. The cooling unit is detachably mounted on the housing of the probe unit, and cools the heat transfer member by passing a coolant in a channel formed inside the cooling unit.

Abstract: According to one embodiment, an ultrasonic probe includes a probe unit and cooling unit. The probe unit is obtained by arranging, in a housing, a transducer unit which transmits and receives ultrasonic waves with an object to be examined, an electronic circuit unit which is connected to the transducer unit and performs electrical signal processing, and a heat transfer member which is made of a material having a heat transfer coefficient higher than that of the electronic circuit unit, and transfers heat of the electronic circuit unit to a housing surface. The cooling unit is detachably mounted on the housing of the probe unit, and cools the heat transfer member by passing a coolant in a channel formed inside the cooling unit.

Abstract: After an ultrasonic diagnosis apparatus is temporally placed on the receptacle of a docking cart to relieve a weight load, the portable ultrasonic diagnosis apparatus is placed at a predetermined position by sliding the apparatus while guiding it along the shapes of the edges of the receptacle. After the portable ultrasonic diagnosis apparatus is slid on the receptacle and rear foot portions come into contact with the stoppers of the receptacle, the front side of the portable ultrasonic diagnosis apparatus is placed on the receptacle. With this operation, front foot portions are fitted in fitting portions, and the portable ultrasonic diagnosis apparatus is placed at an accurate position on the receptacle. In addition, when an operator places the portable ultrasonic diagnosis apparatus on the receptacle or lifts the portable ultrasonic diagnosis apparatus from the receptacle, the fingers which grasp the apparatus are placed in the recessed portions of the receptacle.

Abstract: In a method and a device for accessing an optical disc such as a Compact Disc, a CD-ROM, a CD-I and a MD, an optical disc in which data is recorded or to be recorded at a constant linear velocity is rotated at a substantially constant number of revolution per unit time and this optical disc is accessed on the basis of a clock signal which changes its frequency in accordance with an access position (i.e., a read position or write position). Since random accessing is made in a state in which the optical disc is rotated at a substantially constant number of revolution per unit time, it is not necessary to wait in accessing until a stable revolution number is attained but the waiting time is determined only by time required for moving of the read head. This enables the waiting time to be reduced and thereby realizes accessing to the optical disc at a higher speed.

Abstract: A video display control system displays a multicolor animation pattern on a screen of a video display unit. The video display control system is mainly constructed by a video RAM (VRAM) and a video display processor (VDP). The VRAM stores animation pattern data, display position data and at least two color data. The VDP reads these data and makes an animation pattern image displayed in at least two colors at a display position on the screen. The animation pattern image, two colors and display position are determined by the animation pattern data, two color data and display position data. In another video display control system, the VRAM stores at least two sets of animation pattern data, display position data and color data. When displaying two animation patterns, the VDP effects a logical operation on the two color data with respect to the overlapping portion of the two patterns and makes the overlapping portion displayed in a new color corresponding to the operation result.

Abstract: A data processing system processes digital information representing, for example, an image and supplied at a lower transfer rate from a data source such as an optical disc unit, to produce data in such a form as to be efficiently used by a device of a higher transfer rate such as a CRT display unit. The digital information includes a plurality of groups of data each representing, for example, a portion or a window of the image and added with control data for defining characteristics thereof. While the digital information is read out at a constant entire transfer rate, the plurality of groups of data are transferred at respective transfer rates which vary with a lapse of time. The control data of each group of data is separated therefrom, and the group of data and the separated control data are stored into first and second memories.

Abstract: A video display control system is capable of moving a part of a still image from a first display area to a second display area on a screen. The video display control system includes a memory composed of a plurality of memory locations for storing a plurality of display data representative of images of display elements on the screen. First and second registers retain first and second area data representative of the first and second display areas, and an address data generator generates from these area data first and second address data, the first address data indicating memory locations which store display data corresponding to the first display area, the second address data indicating second memory locations which store display data corresponding to the second display area.

Abstract: A video display control system displays a multicolor animation pattern on a screen of a video display unit. The video display control system is mainly constructed by a video RAM (VRAM) and a video display processor (VDP). The VRAM stores animation pattern data, display position data and at least two color data. The VDP reads these data and makes an animation pattern image displayed in at least two colors at a display position on the screen. The animation pattern image, two colors and display position are determined by the animation pattern data, two color data and display position data. In another video display control system, the VRAM stores at least two sets of animation pattern data, display position data and color data. When displaying two animation patterns, the VDP effects a logical operation on the two color data with respect to the overlapping portion of the two patterns and makes the overlapping portion displayed in a new color corresponding to the operation result.

Abstract: A video display processor (VDP) is connectable to an input control device such as a light pen and a mouse. The VDP comprises a counter circuit which is composed of an X counter and a Y counter. When a mouse mode is selected, X and Y pulse signals are supplied to the X and Y counters so that the contents of the X and Y counters represent the amount of movement of the mouse. When a central processing unit (CPU) connected to the VDP reads the contents of the X and Y counters in this mouse mode, the X and Y counters are reset. When a light pen mode is selected, the X and Y counters effect a count operation of a clock signal generated in the VDP in synchronism with the display of image on a screen so that the contents of the X and Y counters represents X-Y coordinates of a display element which is currently displayed on the screen.

Abstract: A video display control system displays a video image composed of a plurality of display elements on a screen of a video display unit. The system comprises a memory (VRAM) for storing a plurality of color codes each representing at least one display element and a video display controller (VDP). The VDP comprises a mode register for selecting one of normal display and transparency processing modes, display processing circuit for reading the color codes from the VRAM, a backdrop color register for storing a color code such as one representing a backdrop color, a detection circuit for detecting a predetermined color code from the color codes read by the display processing circuit, and a selector controlled by an output of the detection circuit. In the normal display mode, the selector outputs all color codes read by the display processing circuit to the display unit.

Abstract: A video display processor (VDP) produces a video signal by which a black and white image of an increased gradation can be displayed on a video display unit. The VDP reads from a video RAM (VRAM) either color codes each representative of a color of each display element, or amplitude data representative of amplitudes of a video signal to be reproduced. When displaying an image based on the color codes, the color codes are converted by a color palette circuit into color data each composed of three primary color data, and then supplied to a digital color encoder. The digital color encoder multiplies each of the three color data by predetermined coefficients at proper phase timings to output data representative of three chrominance signals. This output data is summed by an adder circuit and then converted into an analog signal to be supplied to the video display unit as the video signal. When displaying an image based on the amplitude data, the color palette circuit converts the amplitude data into gradation data.

Abstract: There is provided a video display controller which can vertically and horizontally shift a whole video image displayed on a screen of a video display unit. The video display controller comprises an image data read circuit which reads the image data from a video RAM, a register into which data representative of amount of shift of the video image is stored by a central processing unit, and a first counter which cyclicly counts a clock signal. An adder adds the data contained in the register and a count output of the first counter, and at a timing determined by this addition result a predetermined value is preset into a second counter. This second counter counts the clock signal from the predetermined value, and the image data read by the image data read circuit is outputted to the video display unit at a timing in accordance with a count output of this second counter. The register, first counter, adder and second counter are provided in each of vertical and horizontal scanning control circuits.

Abstract: A video display control system for displaying a video image on a screen of a video display unit. This video display control system basically comprises a VRAM (video RAM) and a video display processor (VDP). The VRAM has memory locations corresponding to display elements on the screen. The VDP includes a first register for receiving area information identifying a display area on the screen, an address generator for generating addresses of memory locations corresponding to the display area in accordance with the area information, and a memory accessing circuit for accessing the memory locations having the addresses. Therefore, the memory accessing operation through this VDP does not need a complicated support by a central processing unit. The VDP further comprises a second register for storing a color code supplied from an external device or read from the VRAM.

Abstract: A video display controller is provided with a color palette circuit which is capable of converting, at a high conversion rate, color codes read from a VRAM (video RAM) into RGB color data to be supplied to a CRT display unit. The color palette circuit comprises a plurality of color data registers each storing one RGB color data and is supplied with a timing signal synchronized with the display timing of display elements on the CRT display screen. Each color code data including at least two color codes and read from an address of the VRAM is first supplied to a selection circuit which includes at least two decoders. Each decoder decodes the corresponding color codes to generate a selection signal which enables one of the color data registers to output the RGB color data contained therein.

Abstract: A video display processor (VDP) for use with a central processing unit, a video RAM (VRAM) and a video display unit is capable of writing video image data supplied from an external video device such as a television set into the VRAM. The VDP comprises a first input terminal for receiving the external video image data and a second input terminal for receiving horizontal and vertical synchronization signals from the external video device. The VDP generates address data in accordance with the horizontal and vertical synchronization signals and supplies the address data to the VRAM when processing of the external video image data is designated. The VDP also supplies the received external video image data to the VRAM thereby to write the external video image data into addresses of the VRAM designated by the address data.

Abstract: A video display controller which can display foregrounds as well as backgrounds of display patterns on a screen of a video display unit in a plurality of colors. The video display controller comprises a plurality of color information registers, in each of which a pair of color code data representative of foreground and background colors of one display pattern are stored. A memory is provided for storing a plurality of pattern data, a plurality of pattern name data each designating one of the display patterns to be displayed on a respective one of display portions of the screen, and a plurality of color selection data each corresponding to a respective one of the display portions. A sequence controller sequentially reads the pattern data designated by the pattern name data and the color selection data in accordance with synchronization signals.

Abstract: A video display control system comprises a video display processor (VDP) which is capable of accessing to a video RAM (VRAM) at an extremely high-speed. The VRAM used in this system comprises first and second dynamic RAMs each having an address input terminal to which row address data and column address data are supplied, a row address strobe input terminal, a column address strobe input terminal, and a data input/output terminal. The row address data is latched at the leading edge of a row address strobe signal applied to the row address strobe input terminal, while the column address data is latched at the leading edge of a column address strobe signal applied to the column address strobe input terminal. An access to an address of each dynamic RAM is established when both of the row and column address data are latched. The VDP comprises a VRAM interface for controlling an access to the first and second dynamic RAMs which is connected to the RAMs through a common address bus.

Abstract: An electronic musical instrument are provided a plurality of tone production channels to produce musical tones polyphonically. Each of the tone production channel includes a first counter which divides clock pulses by either one of N and N+1 to deliver an output pulse. A second counter and a control circuit are further provided in the instrument, which are commonly used for respective tone production channels. The second counter counts, on the time division basis, the output pulses from the first counters, and the control circuit designates the dividing number of the first counter is relation with the counted value of the second counter. Each of the tone production channels produces a tone signal having a frequency predetermined by the combination of N and N+1. By time divisionally using the second counter and the control circuit, the construction of the instrument is simplified.

Abstract: An automatic performing apparatus for use in an electronic musical instrument stores chord name data and chord generation timing data to carry out an automatic chord performance. In spite of frequent variations of a chord during the progression of a music piece, repetitive storage of a same chord name data is not required so that the amount of stored data can be reduced, allowing utilization of a memory of a small capacity.

Abstract: An electronic musical instrument includes a plurality of address generators for producing address signals corresponding to different tones each varying at a rate synchronous with the frequency of each of the different tones, a waveform memory device including a plurality of addresses for storing at respective addresses a plurality of waveform sample values that constitute a waveform, a circuit for sequentially supplying one after another of the address signals to the waveform memory device to read out the waveform in different rates in a time division multiplexed manner for different tones, and musical tone forming circuits for forming musical tones in accordance with the time division multiplexed waveform outputs of the waveform memory device.