Abstract: A mounting structure of an electronic component includes a plurality of joining portions that join a plurality of first electrode terminals on the electronic component to a plurality of second electrode terminals on a circuit board. The joining portions each include a first projecting electrode formed on the first electrode terminal, a second projecting electrode formed on the second electrode terminal, and a solder portion that joins the first projecting electrode to the second projecting electrode. The end face of the first projecting electrode is larger in area than the end face of the second projecting electrode, and at least a part of the second electrode terminals exposed from the circuit board has a larger area than the bottom of the second projecting electrode.

Abstract: A mounting structure of an electronic component includes a plurality of joining portions that join a plurality of first electrode terminals on the electronic component to a plurality of second electrode terminals on a circuit board. The joining portions each include a first projecting electrode formed on the first electrode terminal, a second projecting electrode formed on the second electrode terminal, and a solder portion that joins the first projecting electrode to the second projecting electrode. The end face of the first projecting electrode is larger in area than the end face of the second projecting electrode, and at least a part of the second electrode terminals exposed from the circuit board has a larger area than the bottom of the second projecting electrode.

Abstract: A multilayer semiconductor device includes an interconnect substrate provided with first electrode lands and connection terminals on a top surface; a semiconductor chip mounted on the top surface of the interconnect substrate; first connecting members connecting the first electrode lands to a circuit formation surface of the semiconductor chip; first metal posts provided on the connection terminals; encapsulating resin filling a space between the interconnect substrate and the semiconductor chip; a package provided with second electrode lands on a main surface; and second connecting members electrically connecting the first metal posts to the second electrode lands.

Abstract: A semiconductor device in which a chip 10 is mounted on a board, includes: a pad group A provided on the chip 10 and electrically connected to an internal circuit in the chip 10; and a test pad pattern B provided on a region of the chip 10 except for a region of the chip 10 where the pad group A is provided. The pad group A includes: pads 12a formed on a principal surface of the chip 10; bumps 16a respectively formed on the pads 12a with a barrier metal layer interposed therebetween, and electrically connected to the board. The test pad pattern B includes: test pads 12b formed on the principal surface of the chip 10; test bumps 16b respectively formed on the test pads 12b with a test barrier metal layer interposed therebetween, and interconnects 11b electrically connecting adjacent ones of the test pads 12b.

Abstract: A multilayer semiconductor device includes an interconnect substrate provided with first electrode lands and connection terminals on a top surface; a semiconductor chip mounted on the top surface of the interconnect substrate; first connecting members connecting the first electrode lands to a circuit formation surface of the semiconductor chip; first metal posts provided on the connection terminals; encapsulating resin filling a space between the interconnect substrate and the semiconductor chip; a package provided with second electrode lands on a main surface; and second connecting members electrically connecting the first metal posts to the second electrode lands.

Abstract: A first insulation film having a first opening is provided on an electrode pad of a semiconductor chip. A second insulation film having a second opening is provided on the first insulation film. A ground metallic layer which is to be in contact with the electrode pad via the first opening is provided on the first insulation film. A bump which is to be mechanically and electrically connected to the ground metallic layer is provided. Further, the above placement is made in a way that the ground metallic layer is provided in the second opening, and the ground metallic layer is provided on an inner side than an outer periphery of the electrode pad, covering the first opening.

Abstract: A semiconductor device includes: a connection electrode formed on a side of a semiconductor element substrate opposed to a bump, where the semiconductor element substrate includes a semiconductor element; a passivation layer covering the semiconductor element substrate and an end portion of the connection electrode; and a barrier metal layer covering the connection electrode and a portion of the passivation layer so as to be electrically connected to the bump. A recess is formed in a portion of the passivation layer connected with the barrier metal layer.

Abstract: A semiconductor device in which a chip 10 is mounted on a board, includes: a pad group A provided on the chip 10 and electrically connected to an internal circuit in the chip 10; and a test pad pattern B provided on a region of the chip 10 except for a region of the chip 10 where the pad group A is provided. The pad group A includes: pads 12a formed on a principal surface of the chip 10; bumps 16a respectively formed on the pads 12a with a barrier metal layer interposed therebetween, and electrically connected to the board. The test pad pattern B includes: test pads 12b formed on the principal surface of the chip 10; test bumps 16b respectively formed on the test pads 12b with a test barrier metal layer interposed therebetween, and interconnects 11b electrically connecting adjacent ones of the test pads 12b.

Abstract: A first insulation film having a first opening is provided on an electrode pad of a semiconductor chip. A second insulation film having a second opening is provided on the first insulation film. A ground metallic layer which is to be in contact with the electrode pad via the first opening is provided on the first insulation film. A bump which is to be mechanically and electrically connected to the ground metallic layer is provided. Further, the above placement is made in a way that the ground metallic layer is provided in the second opening, and the ground metallic layer is provided on an inner side than an outer periphery of the electrode pad, covering the first opening.

Abstract: The present invention provides a semiconductor device in which the warp of a board is suppressed without the need for provision of a solder resist on opposite surfaces of the board and semiconductor element connection characteristics are improved by reducing stress exerted on a connection portion, and increases flexibility in assembly process.

Abstract: According to the present invention, one or more reinforcing vias (7) or reinforcing metal layers are disposed on the inner side of connecting electrodes (5). With this configuration, strength increases relative to a load applied for mounting a semiconductor element (3) and the sinking of the connecting electrodes (5) is reduced. Thus, it is possible to reduce the connecting stress of the semiconductor device, reduce the deformation of a joint, and increase flexibility in process design.