Abstract: A multiprocessor system includes a plurality of processors, each including a task scheduler that determines a task execution order of tasks in a task set to be executed by the processors within a task period which is defined as a period in repeated execution of the task sets; and a scheduler management device having a command unit configured to issue a command for at least one of the task schedulers to change the task execution order, wherein each of the at least one of the task schedulers, when receiving the command from the command unit, changes the task execution order of the corresponding processor.

Abstract: An address conversion apparatus includes a TLB, and an address conversion control section configured to count a consecutive address number indicating the number of consecutive addresses from a pair of a logical address and a physical address stored in the TLB with reference to an address conversion table, store the consecutive address number in association with the pair of the logical address and the physical address, determine whether a conversion target address is included in a range of the consecutive address number from the logical address stored in the TLB or not, and add, if the conversion target address is included in the range, a difference between the logical address and the conversion target address to the physical address which forms a pair with the logical address to calculate a converted physical address.

Abstract: A DMA transfer control device includes a setting register group for setting transfer informations, a number-of-transfers register to which the number of transfers to be performed is set, and which updates a value thereof every time one DMA transfer is completed, a transfer control unit, a secondary setting register group for setting other transfer informations different from the transfer informations, and a specified ordinal-number-of-transfer register. Every time one DMA transfer is initiated, either a value of the setting register group or a value of the secondary setting register group is selected for each of the transfer informations in accordance with a result of an arithmetic operation between a value of the number-of-transfers register and a value of the specified ordinal-number-of-transfer register, and inputted to the transfer control unit. As a result, by making settings for one DMA transfer, it is possible to temporarily change the transfer informations.

Abstract: A DMA transfer control apparatus comprises an internal memory for temporarily storing data, a buffer for temporarily storing data, a selector for selecting one of input data to the buffer and output data from the buffer per byte, and a rotator for rotating data. The internal memory receives read data from a transfer source, the buffer receives data from the internal memory, the selector receives data from the internal memory and data from the buffer, and the rotator receives data selected by the selector. An output of the rotator is used as write data. Thereby, high-speed DMA transfer is performed even when data transfer source addresses and data transfer destination addresses have different byte alignments where the addresses are located.

Abstract: When data is transferred to an access destination in a different endian format, a transfer start address is aligned based on a transfer bus width, and a transfer size is adjusted according to the transfer bus width and a transfer address. Thus, it becomes possible to perform burst transfer in the access destination. Accordingly, in the case where burst transfer to an access destination in a different endian format is performed with a smaller data width than a transfer bus width, an inconvenience where burst transfer can not be performed because an address is converted and data access is no longer an ascending order access can be prevented.

Abstract: A DMA transfer control device includes a setting register group for setting transfer informations, a number-of-transfers register to which the number of transfers to be performed is set, and which updates a value thereof every time one DMA transfer is completed, a transfer control unit, a secondary setting register group for setting other transfer informations different from the transfer informations, and a specified ordinal-number-of-transfer register. Every time one DMA transfer is initiated, either a value of the setting register group or a value of the secondary setting register group is selected for each of the transfer informations in accordance with a result of an arithmetic operation between a value of the number-of-transfers register and a value of the specified ordinal-number-of-transfer register, and inputted to the transfer control unit. As a result, by making settings for one DMA transfer, it is possible to temporarily change the transfer informations.

Abstract: A read data counter counts an unread data amount which is a data amount not yet transferred by adding, whenever a read command is issued, a read data amount which should be acquired by the read command and counting down whenever data is read. A read command issue control unit determines whether or not a determination amount of read command reject which is obtained by subtracting the unread data amount from the free space of the internal memory is equal to or more than a read data amount of the following acquisition target, and allows the issue of the read command when the determination result is affirmative.

Abstract: A DMA transfer control apparatus comprises an internal memory for temporarily storing data, a buffer for temporarily storing data, a selector for selecting one of input data to the buffer and output data from the buffer per byte, and a rotator for rotating data. The internal memory receives read data from a transfer source, the buffer receives data from the internal memory, the selector receives data from the internal memory and data from the buffer, and the rotator receives data selected by the selector. An output of the rotator is used as write data. Thereby, high-speed DMA transfer is performed even when data transfer source addresses and data transfer destination addresses have different byte alignments where the addresses are located.

Abstract: When data is transferred to an access destination in a different endian format, a transfer start address is aligned based on a transfer bus width, and a transfer size is adjusted according to the transfer bus width and a transfer address. Thus, it becomes possible to perform burst transfer in the access destination. Accordingly, in the case where burst transfer to an access destination in a different endian format is performed with a smaller data width than a transfer bus width, an inconvenience where burst transfer can not be performed because an address is converted and data access is no longer an ascending order access can be prevented.