Abstract: A compound semiconductor switching device is based on a designing guideline that isolation should be assured by reducing the gate width of switching FET, thereby reducing the capacitance of the FET. Proper isolation between the two signal passes IS obtained with a FET gate width of about 700 ?m or smaller at a signal frequency of about 2.4 GHz or higher, without employing a shunt FET.

Abstract: The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 ?m for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 ?m or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 ?m or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer.

Abstract: A binder (10) has a base (14) having passages (14A, 14A) through which binding legs (13,13) can be inserted. The base (14) has a plurality of base-forming members (17,17) that can move relative to each other along the longitudinal direction. Each of the base-forming members (17,17) has first and second operating portions (22,23) that move when the base-forming members (17,17) are moved relative to each other. The second operating portions (23,23) move away from each other and press the binding legs (13,13) onto their binding positions when the first operating portions (22,22) are moved toward each other. The binding legs (13,13) are released and the first operating portions (22,22) move away from each other when the second operating portions (23,23) are moved toward each other.

Abstract: A binder comprises an operating member supported on a base, a pressing member movable toward and away from the base by the movement of the operating member, and locking means for locking the operating member when the pressing member is set in a binding position. The operating member has a first operating spot and a second operating spot, and the operating member is locked to hold the pressing member at the binding position when the first operating spot is pressed toward the surface of the base, and unlocked to move the pressing member away from the base when the second operating spot is operated similarly.

Abstract: The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 &mgr;m for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 &mgr;m or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 &mgr;m or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer.

Abstract: The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 &mgr;m for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 &mgr;m or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 &mgr;m or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer.

Abstract: A binder 10 has a base 14 having passages 14A, 14A through which binding legs 13, 13 can be inserted. The base 14 has a plurality of base-forming members 17, 17 that can move relative to each other along the longitudinal direction. Each of the base-forming members 17, 17 has first and second operating portions 22, 23 that move when the base-forming members 17, 17 are moved relative to each other. The second operating portions 23, 23 move away from each other and press the binding legs 13, 13 onto their binding positions when the first operating portions 22, 22 are moved toward each other. The binding legs 13, 13 are released and the first operating portions 22, 22 move away from each other when the second operating portions 23, 23 are moved toward each other.

Abstract: The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 &mgr;m for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 &mgr;m or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 &mgr;m or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer.

Abstract: A compound semiconductor switching device is based on a designing guideline that isolation should be assured by reducing the gate width of switching FET, thereby reducing the capacitance of the FET. Proper isolation between the two signal passes IS obtained with a FET gate width of about 700 &mgr;m or smaller at a signal frequency of about 2.4 GHz or higher, without employing a shunt FET.

Abstract: A binder comprises an operating member supported on a base, a pressing member movable toward and away from the base by the movement of the operating member, and locking means for locking the operating member when the pressing member is set in a binding position. The operating member has a first operating spot and a second operating spot, and the operating member is locked to hold the pressing member at the binding position when the first operating spot is pressed toward the surface of the base, and unlocked to move the pressing member away from the base when the second operating spot is operated similarly.

Abstract: A negative voltage generating circuit includes an oscillating unit constructed of a ring oscillator for outputting a pulse signal with a high frequency and a polarity inverting unit in which the pulse signal is inputted to charge negative voltage. This negative voltage generating circuit is miniaturized and outputs a stable negative voltage. Further, the negative voltage to be outputted can be controlled by varying a resistance value through a control of an FET in a voltage controlling unit.

Abstract: A group III-V compound semiconductor doped with an impurity, having an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed on a crystal of Group III-V compound semiconductor in which the silicon in the SiOx film is diffused into the Group III-V compound semiconductor, thereby forming a doped layer.

Abstract: A method of doping a Group III-V compound semiconductor with an impurity, wherein after an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed in this order on a crystal of Group III-V compound semiconductor, the sample is subjected to at least one heat treatment to cause silicon in the SiOx film to diffuse into the Group III-V compound semiconductor, thereby forming a doped layer. Using this doped layer forming method, field-effect transistors, diodes, resistive layers, two-dimensional electron gas or one-dimensional quantum wires, zero-dimensional quantum boxes, electron wave interference devices, etc. are fabricated.

Abstract: A field-effect transistor including a first channel layer, formed in contacting relationship with a gate electrode, and a second channel layer, formed on one side or both sides of the first channel layer in non-contacting relationship with the gate electrode, the carrier concentration in the second channel layer being higher than that in the first channel layer but lower than that in high-impurity concentration active layers forming drain and source regions. The field-effect transistor employs an offset gate configuration in which the gate electrode is formed in contacting relationship with the first channel layer at a position nearer to the high-impurity concentration active layer forming the source region than to the high-impurity concentration active layer forming the drain region.