Patents by Inventor Takayuki Gomi
Takayuki Gomi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5629217Abstract: A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.Type: GrantFiled: October 6, 1994Date of Patent: May 13, 1997Assignee: Sony CorporationInventors: Hiroyuki Miwa, Takayuki Gomi, Katsuyuki Kato
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Patent number: 5622887Abstract: A semiconductor device comprising a MIS structure comprising a first electrically conductive film formed on an oxide film, a second electrically conductive film formed on at least a part of said first electrically conductive film, an insulator film formed on said second electrically conductive film, and a third electrically conductive film formed on said insulator film; and at least one electrode contact portion formed on said first electrically conductive film. A semiconductor device comprising a MIS capacitor having a diffusion layer inside the semiconductor substrate as a lower electrode with a first electrically conductive type being isolated using another diffusion layer having the opposite conductive type, and said another diffusion layer having the opposite conductive type being further isolated using a diffusion layer for isolation having the first conductive type and which is earthed.Type: GrantFiled: October 17, 1994Date of Patent: April 22, 1997Assignee: Sony CorporationInventors: Hiroyuki Miwa, Mamoru Shinohara, Takayuki Gomi, Tomotaka Fujisawa
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Patent number: 5580797Abstract: A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.Type: GrantFiled: May 18, 1994Date of Patent: December 3, 1996Assignee: Sony CorporationInventors: Hiroyuki Miwa, Takayuki Gomi, Katsuyuki Kato
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Patent number: 5548156Abstract: A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.Type: GrantFiled: March 7, 1995Date of Patent: August 20, 1996Assignee: Sony CorporationInventors: Hiroyuki Miwa, Takayuki Gomi, Katsuyuki Kato
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Patent number: 5541124Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.Type: GrantFiled: June 7, 1995Date of Patent: July 30, 1996Assignee: Sony CorporationInventors: Hiroyuki Miwa, Shigeru Kanematsu, Takayuki Gomi, Hiroaki Anmo, Takashi Noguchi, Katsuyuki Kato, Hirokazu Ejiri, Norikazu Ouchi
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Patent number: 5414291Abstract: A semiconductor device comprising a MIS structure comprising a first electrically conductive film formed on an oxide film, a second electrically conductive film formed on at least a part of said first electrically conductive film, an insulator film formed on said second electrically conductive film, and a third electrically conductive film formed on said insulator film; and at least one electrode contact portion formed on said first electrically conductive film. A semiconductor device comprising a MIS capacitor having a diffusion layer inside the semiconductor substrate as a lower electrode with a first electrically conductive type being isolated using another diffusion layer having the opposite conductive type, and said another diffusion layer having the opposite conductive type being further isolated using a diffusion layer for isolation having the first conductive type and which is earthed.Type: GrantFiled: January 31, 1994Date of Patent: May 9, 1995Assignee: Sony CorporationInventors: Hiroyuki Miwa, Mamoru Shinohara, Takayuki Gomi, Tomotaka Fujisawa
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Patent number: 5391503Abstract: According to this invention, a base extracting electrode is formed using a polysilicon side wall self-aligned with a base region so as to reduce a collector-base parasitic capacitance of a transistor. A base layer is formed on a semiconductor substrate by a selective epitaxial method using an MBE method to obtain a high-speed operation. A high impurity-concentration region is formed on a buried layer immediately below an emitter by pedestal ion implantation to reduce a collector series resistance. In addition, a specific layer of a plurality of polysilicon layers is selectively annealed by radiation of an eximer laser to operate the transistor at high speed and to obtain a highly accurate resistor element.Type: GrantFiled: September 4, 1992Date of Patent: February 21, 1995Assignee: Sony CorporationInventors: Hiroyuki Miwa, Takayuki Gomi, Takashi Noguchi, Norikazu Ohuchi
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Patent number: 5389561Abstract: The present invention is directed to a SOI type bipolar transistor and a method of making the transistor. The transistor comprises an element forming region, which is surrounded on its side portions and a lower surface portion by an insulating layer, an emitter region, a base region, a collector region, each of the emitter, base and collector regions being disposed within the element forming region, and a semiconductor layer formed on the element forming region at a portion corresponding to an opening portion of an interlayer and which becomes an emitter diffusion layer, so that a part of the semiconductor layer is grown under the condition that the semiconductor layer is overgrown over the interlayer in the lateral direction, a junction surface between the base region and the collector region exists under the overgrown portion of the semiconductor layer and the emitter region is surrounded on its side portions and its lower portion by the base region.Type: GrantFiled: December 2, 1993Date of Patent: February 14, 1995Assignee: Sony CorporationInventor: Takayuki Gomi
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Patent number: 5163178Abstract: A semiconductor device comprises a semiconductor substrate provided with a collector region a base region and an emitter region in a lateral arrangement. Respective portions having peak impurity concentrations of the collector region and the emitter region are formed within the semiconductor substrate. A method of fabricating a semiconductor device comprises a step of forming a collector region of a second conduction type and an emitter region of a second conduction type in a lateral arrangement in a semiconductor substrate serving as a base region of a first conduction type by using a first mask provided with a pair of openings, and a step of forming heavily doped regions of the second conduction type so as to be connected respectively to the collector region and the emitter region by using a second mask provided with a pair of openings separated from each other by a distance greater than the distance between the openings of the first mask.Type: GrantFiled: December 27, 1990Date of Patent: November 10, 1992Assignee: Sony CorporationInventors: Takayuki Gomi, Minoru Nakamura, Hiroaki Anmo, Norikazu Chuchi, Hiroyuki Miwa, Akio Kayanuma, Koji Kobayashi
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Patent number: 5010026Abstract: A bipolar transistor has a base region consisting of a graft base region, linking base region and an intrinsic base region, and a diffusion suppressing region of an opposite conductivity type to that of the base region is formed at least at the lower portion of the intrinsic base region. The junction depth of the linking base region is selected to be shallower than that of the intrinsic base region. Since the base to base linking is performed in the linking base region, collision between the intrinsic base region and the graft base region is inhibited, while the diffusion of the base width beyond the diffusion suppressing region is also inhibited. The junction depth of the linking base region is selected to be shallow to prevent the width of the parasitic base from being increased to suppress the side injection effect.Type: GrantFiled: August 10, 1989Date of Patent: April 23, 1991Assignee: Sony CorporationInventor: Takayuki Gomi
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Patent number: 4994881Abstract: An improved bipolar transistor is a vertical type bipolar transistor the base region of which is composed of a graft base region, an intrinsic base region separated from the graft base region and having an emitter region in its inside, and a link impurity diffusion region linking these regions. In the preparation, the graft base region is formed by diffusion of impurities from the base contact electrode layer and the emitter region formed in the intrinsic base region may be formed in self-alignment. In the vicinity of the junction between the base region and the semiconductor substrate, there is formed a diffusion suppression region composed of an impurity diffusion region of a conductivity type opposite to the conductivity type of the base region and adapted for preventing the depth of junction from being increased.Type: GrantFiled: February 13, 1989Date of Patent: February 19, 1991Assignee: Sony CorporationInventor: Takayuki Gomi
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Patent number: 4844312Abstract: In an apparatus for controlling a traverse direction of a running strip, a deviation of the running strip in the traverse direction with respect to a reference position is calculated, and the running strip is moved in the transverse direction in accordance with the deviation, thereby correcting the traverse position of the running strip.Type: GrantFiled: January 27, 1988Date of Patent: July 4, 1989Assignee: Kitamura Kiden Co., Ltd.Inventors: Takayuki Gomi, Fumio Kitamura