Abstract: When a polymer gel has excellent mechanical strength and an ability to maintain surface wetness for a longer time, the polymer gel may be very widely applied to a variety of fields. The present disclosure provides example embodiments of a polymer gel having excellent mechanical strength and an ability to maintain surface wetness for a longer time. Further, the present disclosure provides example embodiments of a method of preparing the polymer gel.

Abstract: A composite containing a fabric and a polyampholyte hydrogel is provided. In the composite, the polyampholyte hydrogel is a hydrogel of a polymer containing randomly dispersed cationic and anionic repeat groups and at least a part of the fabric is coated with the polyampholyte hydrogel. A method of preparation of the composite involves steps (a) to (c): (a) providing a monomer mixture for preparation of a polyampholyte hydrogel; (b) immersing a fabric in the monomer mixture solution; and (c) polymerizing monomers in the monomer mixture solution to obtain a precursor of the composite.

Abstract: An aqueous gel that is prepared by gelling a polymer components, the polymer components containing polymer A, which is obtained by polymerizing a monomer component containing a betaine monomer represented by the formula (I): wherein R1 represents hydrogen atom or an alkyl group, R2 represents an alkylene, arylene, aralkylene, —COOH- or —CONH-group; R3 and R4 represent an alkyl group, and R5 represents an alkylene group, and a polymer B, which is obtained by polymerizing a monomer component containing an acidic monomer represented by the formula (II): wherein R1 represents hydrogen atom or an alkyl group; R6 represents an optionally neutralized sulfonate group, an optionally neutralized phosphate group, or an alkyl, aryl, aralkyl, carboxyl or amino group carrying an optionally neutralized sulfonate group or an optionally neutralized phosphate group.

Abstract: A semiconductor device includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a layer and another one of the ground lines extending from the one of the ground lines toward another direction in the layer, a first pad on the multi-layer wiring layer, and a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first pad and the second pad, and an insulation film covering the redistribution line.

Abstract: A semiconductor device, includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a predetermined layer and another one of the ground lines extending from the one of the ground lines toward another direction in the predetermined layer, a first pad on the multi-layer wiring layer, a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first and second pads, and an insulation film covering the redistribution line, the redistribution line extending above the ground lines along the one of the ground lines and not extending along the another one of the ground lines. The insulation film includes a hole exposing the second pad above an end portion of the one of the ground lines.

Abstract: A semiconductor device, includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a predetermined layer and another one of the ground lines extending from the one of the ground lines toward another direction in the predetermined layer, a first pad on the multi-layer wiring layer, a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first and second pads, and an insulation film covering the redistribution line, the redistribution line extending above the ground lines along the one of the ground lines and not extending along the another one of the ground lines. The insulation film includes a hole exposing the second pad above an end portion of the one of the ground lines.

Abstract: A semiconductor integrated circuit device includes a first chip including an internal circuit, and a second chip capable of being accessed only via the first chip, and a test processor circuit electrically connected internally via the first chip, for accessing the second chip from an external terminal and testing the second chip, and a test circuit where an input/output buffer is installed for signals for accessing the second chip within the test processor circuit, and a bypass line installed for transferring signals from the first chip to the second chip and avoiding the input/output buffer within the test processor circuit, and a switch which switches between signal transfer path via the input/output buffer, and a signal transfer path via the bypass line.

Abstract: A semiconductor device, includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a predetermined layer and another one of the ground lines extending from the one of the ground lines toward another direction in the predetermined layer, a first pad on the multi-layer wiring layer, a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first and second pads, and an insulation film covering the redistribution line, the redistribution line extending above the ground lines along the one of the ground lines and not extending along the another one of the ground lines. The insulation film includes a hole exposing the second pad above an end portion of the one of the ground lines.

Abstract: A semiconductor device includes a substrate over which a circuit is formed, a multi-layer wiring layer having a plurality of wiring layers formed over the substrate and a pad formed in a predetermined location of an uppermost layer of the wiring layers, a new pad provided in an appropriate location over the multi-layer wiring layer, and a redistribution layer provided with a redistribution line coupling the new pad and the pad. In the semiconductor device: the multi-layer wiring layer includes a signal line for transmitting an electric signal to the circuit and a ground line provided in a wiring layer between the redistribution line or the new pad and the circuit; the ground line is formed to correspond to a location where the new pad is assumed to be located and a route along which the redistribution line is assumed to be formed; and the redistribution line is formed along at least a portion of the ground line.

Abstract: A semiconductor device includes a substrate over which a circuit is formed, a multi-layer wiring layer having a plurality of wiring layers formed over the substrate and a pad formed in a predetermined location of an uppermost layer of the wiring layers, a new pad provided in an appropriate location over the multi-layer wiring layer, and a redistribution layer provided with a redistribution line coupling the new pad and the pad. In the semiconductor device: the multi-layer wiring layer includes a signal line for transmitting an electric signal to the circuit and a ground line provided in a wiring layer between the redistribution line or the new pad and the circuit; the ground line is formed to correspond to a location where the new pad is assumed to be located and a route along which the redistribution line is assumed to be formed; and the redistribution line is formed along at least a portion of the ground line.

Abstract: A semiconductor memory device for storing data defining a multidimensional space based on coordinate information of the data, includes: a cell array having memory cells arranged in a lattice pattern, for storing the data; a word line selector selecting and driving any one of a plurality of word lines which activate memory cells arranged in a row direction; write amplifiers/sense amplifiers writing/reading data to/from the memory cells arranged in a column direction; an amplifier selector inputting/outputting the data to/from the selected one of the write amplifiers/sense amplifiers; and an address conversion circuit generating a row address to be supplied to the word line selector based on the coordinate information of the data, and to generate a column address to be supplied to the amplifier selector by converting the coordinate information of the data into one-dimensional information.

Abstract: A semiconductor integrated circuit device includes a first chip including an internal circuit, and a second chip capable of being accessed only via the first chip, and a test processor circuit electrically connected internally via the first chip, for accessing the second chip from an external terminal and testing the second chip, and a test circuit where an input/output buffer is installed for signals for accessing the second chip within the test processor circuit, and a bypass line installed for transferring signals from the first chip to the second chip and avoiding the input/output buffer within the test processor circuit, and a switch which switches between signal transfer path via the input/output buffer, and a signal transfer path via the bypass line.

Abstract: According to an aspect of the present invention, there is provided a semiconductor memory device for storing data defining a multidimensional space based on coordinate information of the data, including: a cell array having memory cells arranged in a lattice pattern, for storing the data; a word line selector selecting and driving any one of a plurality of word lines which activate memory cells arranged in a row direction; write amplifiers/sense amplifiers writing/reading data to/from the memory cells arranged in a column direction; an amplifier selector inputting/outputting the data to/from the selected one of the write amplifiers/sense amplifiers; and an address conversion circuit generating a row address to be supplied to the word line selector based on the coordinate information of the data, and to generate a column address to be supplied to the amplifier selector by converting the coordinate information of the data into one-dimensional information.

Abstract: A non-volatile flash memory (100) that may have an improved layout freedom is disclosed. Non-volatile flash memory (100) may include banks (B0 and B1). Each bank (B0 and B1) may include memory cell arrays (MCA00 to MCA03) including a plurality of memory cells (MC) connected to sub bit lines (LB). A plurality of sub bit lines (LB) may be selectively connected to a main bit line (MB) by a group switch (Y1S0 and Y1S1). A group of main bit lines (MB) may be disposed over a memory cell array. A group of main bit lines (MB) may be selectively connected to a sense amplifier block (SAB) by a group switch group (Y2S0 and Y2S1) and a bank switch group (Y3S0 and Y3S1). In this way, a sense amplifier block (SAB) may be shared by a plurality of groups of main bit lines (MB). In this way, layout freedom may be improved.

Abstract: A level shifter (1) that may provide a relatively high-speed operation in a level shifting mode and a non-level shifting mode has been disclosed. Level shifter (1) may include a transistor (P101) providing a controllable current path between a voltage terminal (3) and an output signal (TOUT) based on the logic level of an input signal (IN). Series connected transistors (P104 and P105) may provide a controllable current path between voltage terminal (3) and output signal (TOUT) based on the logic level of an input signal (IN). Transistor (P105) may be enabled in a Vcc mode and may be disabled in a Vpp mode. In this way, an equivalent transistor width (WT) may be adjusted in accordance with a mode of operation and a transition time of output signal (TOUT) may be improved.

Abstract: A non-volatile flash memory (100) that may have an improved layout freedom is disclosed. Non-volatile flash memory (100) may include banks (B0 and B1). Each bank (B0 and B1) may include memory cell arrays (MCA00 to MCA03) including a plurality of memory cells (MC) connected to sub bit lines (LB). A plurality of sub bit lines (LB) may be selectively connected to a main bit line (MB) by a group switch (Y1S0 and Y1S1). A group of main bit lines (MB) may be disposed over a memory cell array. A group of main bit lines (MB) may be selectively connected to a sense amplifier block (SAB) by a group switch group (Y2S0 and Y2S1) and a bank switch group (Y3S0 and Y3S1). In this way, a sense amplifier block (SAB) may be shared by a plurality of groups of main bit lines (MB). In this way, layout freedom may be improved.

Abstract: A level shifter (1) that may provide a relatively high-speed operation in a level shifting mode and a non-level shifting mode has been disclosed. Level shifter (1) may include a transistor (P101) providing a controllable current path between a voltage terminal (3) and an output signal (TOUT) based on the logic level of an input signal (IN). Series connected transistors (P104 and P105) may provide a controllable current path between voltage terminal (3) and output signal (TOUT) based on the logic level of an input signal (IN). Transistor (P105) may be enabled in a Vcc mode and may be disabled in a Vpp mode. In this way, an equivalent transistor width (WT) may be adjusted in accordance with a mode of operation and a transition time of output signal (TOUT) may be improved.

Abstract: A position recognition device that outputs data according to a position has a GPS unit for detecting position, an audio input/output unit for inputting and outputting audio and a memory unit for storing data. Audio data as well as corresponding position data are combined, recorded and stored in the memory unit. When a present position as measured by the GPS unit matches position data stored with the audio data, the position recognition device reproduces the audio data corresponding to the position, making it possible to output essential data at the position.

Abstract: A GPS receiver displays information concerning a distance to a destination and a direction with respect to the destination and the like. The information is provided according to a preset operating condition on the basis of data which include position data of the destination which is set in advance and position data of the current position which is obtained from radio waves emitted from GPS satellites orbiting the earth. The GPS receiver includes a memory which stores data of operating conditions corresponding to first, second, third and fourth operation modes. The parameters of the operating conditions of the four operation modes are different from each other in at least a part thereof.