Abstract: An SCR type memory apparatus which is short in access time, easy in setting current values upon reading and writing and easy in constructing a peripheral circuit with less power supply voltage limitation is described. The semiconductor memory apparatus comprises of a basic cell circuit which includes an SCR type memory cell. The SCR type memory cell includes a pair of pnp transistors and a pair of double emitter transistors. The basic cell circuit also includes a pair of write npn transistors. The collector of each write npn transistor is connected to a voltage holding node of the SCR type memory cell and the base is connected to a word selecting line.

Abstract: In a semiconductor integrated circuit device of master slice approach according to this invention, regions on basic elements which are not used and isolation areas serve as wiring regions. Resistive elements are formed on the regions on the basic elements which are not used and the isolation areas. A high integration level can be obtained, circuit layout can be facilitated, and versatility of circuit design can be improved.