Patents by Inventor Takayuki Morioka

Takayuki Morioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5003458
    Abstract: Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.
    Type: Grant
    Filed: October 23, 1987
    Date of Patent: March 26, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Shinichiro Yamaguchi, Hidekazu Matsumoto, Tadaaki Bandoh, Hirokazu Hirayama, Takayuki Morioka, Soichi Takaya, Yukio Kawamoto, Jushi Ide, Yoshihiro Miyazaki
  • Patent number: 4967339
    Abstract: A processor performs a pipelined parallel processing by an operand effective address calculation unit for calculating an operand effective address necessary to execute an instruction and an instruction execution unit for executing the instruction. A 64 bit width data operation is performed in such a way that a high order 32 bit operation is performed in an arithmetic device in the operand effective address unit and a low order 32 bit operation is performed in another arithmetic device in the instruction execution unit. A carry is transferred from the low order 32 bit arithmetic device to the high order 32 bit arithmetic device. The arithmetic devices thus joined can perform the 64 bit with data operation as an arithmetic device.
    Type: Grant
    Filed: April 8, 1988
    Date of Patent: October 30, 1990
    Assignees: Hitachi, Ltd., Hitachi Engineering, Ltd.
    Inventors: Hiroaki Fukumaru, Soichi Takaya, Takayuki Morioka, Tadaaki Bandoh, Shinichiro Yamaguchi, Kenji Hirose
  • Patent number: 4877558
    Abstract: A method of oxidatively decomposing a radioactive ion-exchange resin is described, the method comprising oxidatively decomposing a radioactive ion-exchange resin containing an anion-exchange resin with hydrogen peroxide used as an oxidizing agent in the presence of iron and copper ions used as catalysts, wherein the weight ratio of hydrogen peroxide to the ion-exchange resin, that is the ratio of the net weight of hydrogen peroxide to the dry weight of the ion-exchange resin containing an anion-exchange resin, is held to be no higher than 17 and the pH of the reaction system is adjusted to be within the range of 0.5 to 6, or citric acid ions are preliminarily adsorbed on the radioactive ion-exchange resin before it is subjected to decomposition treatment or citric acid ions coexist with the radioactive ion-exchange resin in the oxidatively decomposing system, and an apparatus used for conducting the method is also described.
    Type: Grant
    Filed: April 29, 1987
    Date of Patent: October 31, 1989
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Takayuki Morioka, Nobuyuki Motoyama, Hiroshi Hoshikawa, Takeo Takahashi, Sizuo Suzuki, Tuyoshi Ishikawa, Takanori Toyoshi, Toshio Uede
  • Patent number: 4807113
    Abstract: A microprogram controlled data processing apparatus executes multi-operand instructions in which one or more operand specifiers are provided for specifying the addressing for each operand independently from the operation code of the instruction. An instruction execution unit receives a top address of a microprogram from a decoding unit, a ready status signal and a signal from the decoding unit indicating whether a destination of an operand is in a general purpose register or in a memory unit, and writes an operand into a destination address of a register on the memory unit under control of a microprogram. Because the destination of the operand is indicated by the instruction decoding unit, it is not necessary to determine this information by microinstruction execution, with the result that execution of the instruction can be performed at high speed.
    Type: Grant
    Filed: November 14, 1986
    Date of Patent: February 21, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Hidekazu Matsumoto, Tadaaki Bandoh, Ryosei Hiraoka, Takayuki Morioka, Yoshihiro Miyazaki
  • Patent number: 4468733
    Abstract: A multi-computer system includes a plurality of data processors and at least one I/O device which is commonly accessible by the data processors. A plurality of serial bus loops are configurated in hierarchy with interbus linkage devices disposed between adjacent layers of the hierarchy. The data processors are connected to a plurality of first layer serial bus loops and the I/O device which is commonly accessible by the data processors is connected to a second layer of serial bus loop. The interbus linkage devices control linkage among the plurality of serial bus loops and carry out routing control for a start command from the data processor to the I/O device, routing control for an interruption to report the end of I/O device operation, routing control for data transfer, routing control for a request interruption and exclusive use control of the shared I/O device.
    Type: Grant
    Filed: June 4, 1981
    Date of Patent: August 28, 1984
    Assignee: Hitachi, Ltd.
    Inventors: Toshihisa Oka, Hiroaki Nakanishi, Ryoichi Takamatsu, Takayuki Morioka, Masakazu Okada, Hideyuki Hara, Hirokazu Kasashima
  • Patent number: 4200865
    Abstract: A printed circuit board loaded with an electronic circuit and constructed to be capable of being inserted in and withdrawn from a bus line on on-line status, in which the input to or the output from the printed circuit board is locked out in response to the presence of two conditions, one is the presence of a demand for insertion or withdrawal of the printed circuit board on on-line status and the other is the presence of such a condition that no information exchange is being made between the printed circuit board and other unit connected with the bus line, thereby releasing the electrical connection between the bus line and the printed circuit board so that the printed circuit board can now be inserted in or withdrawn from the bus line on on-line status.
    Type: Grant
    Filed: January 27, 1978
    Date of Patent: April 29, 1980
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Morioka, Jushi Ide